Jäger ADwin-Pro, System And Hardware Description

Page: 135 / 218

ADwin-Pro Hardware, manual version 2.9, June 2006
131
Pro I: Digital-I/O- and Counter Modules
Pro-CO4-D Rev. A
ADwin
Fig. 251 – Pro-CO4-D Rev. A : Pin assignment
1 9 - 9 -
2 - 9 - 9
3 - - - -
4 - - - -
Counter 4 multi purpose co
2 SSI decoders
Counter resolution 32 bit
Input/output levels RS422/485 compatible (5V differen-
tial, 120
Ω
bus terminating resistor,
see also block diagram)
Event input 1 differential
(single-ended operation possible)
Reference clock 40MHz (100 ppm)
Clock frequency four edge evaluation 5MHz max. (at 90° phase shift of the
signals)
Clock frequency up/down counter 20MHz max.
Reference frequency PWM analysis 40MHz
Clock frequency SSI decoder (CLK) 1MHz max.
Connector 37-pin DSub socket
Power consumption approx. 200mA
Fig. 252 – Pro-CO4-D Rev. A : Specification
DIP switch
position
Input counter#
A/CLK/PWM
Counter
CNTR-#1 CNTR-#2 CNTR-#3 CNTR-#4
Fig. 250 – Pro-CO4-D Rev. A : Allocation of Input to Counter with DIP switches
SSI 1, CLK (-)
CNTR 1, A/CLK/PWM (-)
CNTR 1, B/DIR (-)
CNTR 1, CLR/LATCH (-)
SSI 1, DATA (-)
CNTR 2, A/CLK/PWM (-)
CNTR 2, B/DIR (-)
CNTR 2, CLR/LATCH (-)
SSI 2, CLK (-)
CNTR 3, A/CLK/PWM (-)
CNTR 3, B/DIR (-)
CNTR 3, CLR/LATCH (-)
SSI 2, DATA (-)
CNTR 4, A/CLK/PWM (-)
CNTR 4, B/DIR (-)
CNTR 4, CLR/LATCH (-)
DGND
EVENT-IN (+)
SSI 1, CLK (+)
CNTR 1, A/CLK/PWM (+)
CNTR 1, B/DIR (+)
CNTR 1, CLR/LATCH (+)
SSI 1, DATA (+)
CNTR 2, A/CLK/PWM (+)
CNTR 2, B/DIR (+)
CNTR 2, CLR/LATCH (+)
SSI 2, CLK (+)
CNTR 3, A/CLK/PWM (+)
CNTR 3, B/DIR (+)
CNTR 3, CLR/LATCH (+)
SSI 2, DATA (+)
CNTR 4, A/CLK/PWM (+)
CNTR 4, B/DIR (+)
CNTR 4, CLR/LATCH (+)
DGND
+5V, <100mA (fused)
EVENT-IN (-)
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7
6
5
4
3
2
1
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