Jäger ADwin-Pro, System And Hardware Description, Page: 139 / 218

ADwin-Pro Hardware, manual version 2.9, June 2006
135
Pro I: Digital-I/O- and Counter Modules
Pro-PWM-4-I Rev. A
ADwin
Fig. 258 – Pro-PWM-4-I Rev. A : Pin assignment
Fig. 259 – Pro-PWM-4-I Rev. A : Board and front panel
Output channels 4
Counter-/register width 16 bit
f
clk
after
Prescaler
Div. by 1 (2
0
) 200ns (5MHz)
Div. by 2 (2
1
) 400ns (2.5MHz)
Div. by 4 (2
2
) 800ns (1.25MHz)
…
Div. by 128 (2
7
) 25.6µs (
≈
39kHz)
Output voltage 5…30V DC
with an external power supply
Output current 100mA max. per channel
Event inputs Pos. TTL
Voltage drop 0.5V max.
Switching time 10µs
Event input 1
Event input voltage 5V, 12V, 24V
(selectable via jumpers)
Connector 37-pin DSub socket
Isolation 42V channel-channel / channel-GND
Fig. 260 – Pro-PWM-4-I Rev. A : Specification
RESERVED
EVENT IN (+)
PWM OUTPUT 1 (+)
PWM OUTPUT 2 (+)
PWM OUTPUT 3 (+)
PWM OUTPUT 4 (+)
EVENT IN (-)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
External GND
External Vcc
RESERVED
RESERVED
RESERVED
RESERVED
19CNT01
ON
1 2 3 4 5 6 7 8
A0 A1 A2 A3 A4 A5 A6 A7
FPGA FPGA
FP
G
A
74A
B
T
16245
74LS19
74LS19
74LS19
74LS19
74LS19
74LS19
74LS19
OCX
FPGA FPGA
DCP010505BP
BC
489
HCPL-2631
HCPL-2631
HCPL-2631
HCPL-2631
BC
489
BC
489
BC
489
BC
489
BC
489
BC
489
BC
489
1N4004
1N4004
1N4004
1N4004
1N4004
1N4004
1N4004
1N4004
+5
V
+1
2
V
+2
4
V
19CNTI01
HCPL-2631
PWM-4-I
PW - OUTPUT
Jumpers for Event