Jäger ADwin-Pro, System And Hardware Description

Page: 138 / 218

Pro I: Digital-I/O- and Counter Modules
Pro-PWM-4-I Rev. A
ADwin
134
ADwin-Pro Hardware, manual version 2.9, June 2006
5.8.21 Pro-PWM-4-I Rev. A
The module Pro-PWM-4-I Rev. A generates pulse width modulated signals
(PWM signals) at four outputs. Each (PWM-) signal can be configured individ-
ually via software, that means they can be configured separately.
The function of the module is significantly characterized by its 4 counters
(16 bit) and 8 registers (16 bit), 4 for the duration of the low voltage level and
4 for the high voltage level.
The counters are clocked by a crystal oscillator with a frequency of 5MHz. By
defining a (scale) register the frequency can be roughly prescaled in 2
n
steps
(0 < n < 7, n
∈
N). By presetting the duration of the high- and low-pulses, the
output frequency of the PWM signals is defined.
The output of the PWM signals is attained by evaluating the register values and
the count rate via an RS-flip-flop.
The inputs are optically isolated from the system circuitry and from other
inputs. The event-input is isolated from the system circuitry as well. The input
voltage range of the counter inputs can be selected by jumpers. The default
setting of the input voltage range is 24V.
By setting a register, the counters can be enabled or disabled. But do not con-
fuse this with enabling or disabling the PWM output (putting it into a "static"
mode). This can only be made by the command
PWM_OUT(…)
, which sets the
output to a defined status, when the counter is enabled.
The lowest output frequency at a still definable duty cycle of approx. 0...100%
is about 0.6Hz.
The highest output frequency where the duty cycle can be still defined in
1%-steps, is 50kHz.
The module Pro-PWM-4-I Rev. A is equipped with 4 times the components
shown in the block diagram; exception: the event input and the 5MHz refer-
ence oscillator, which can only be found once on each module.
Fig. 257 – Pro-PWM-4-I Rev. A : Block diagram
Data
Data
A B
A B
NOTE: Only PWM-output #1 is shown for clarity of the schematic. The 5MHz clock signal is distributed to all prescalers.
G
5 MHz
Prescaler #1
divide by 2 n
(n = 0...7)
Control registers #1
16 bit HIGH-time Register #1
16 bit Counter #1
16 bit LOW-time Register #1
Q
Q
S
R
B
A
A
B
EN
EN
CLK
EN
CLR
ADw
in
-P
ro
bu
s
Data
Data
Data
Data
to other
Prescaler
Da
ta
GND
#1
Vcc
BC489
1N
4001
+
-
EVENT
24V
12V
5V
1k
56
k
56
k
4k3
2k
560