Jäger ADwin-Pro, System And Hardware Description

Page: 73 / 218

ADwin-Pro Hardware, manual version 2.9, June 2006
69
Pro I: Analog Input Modules
Pro-AIn-F-4/14 Rev. B
ADwin
5.5.15 Pro-AIn-F-4/14 Rev. B
Analog input module Pro-AIn-F-4/14 Rev. B with 4 fast-ADC (14 bit) and 4 dif-
ferential inputs.
The inputs are available with the following connectors:
– Pro-AIn-4/14: shielded LEMO-sockets, CAMAC European norm.
– Pro-AIn-4/14-D: DSub socket 37-pin.
The module has 2 operating modes, which you can use optionally for each of
the channels:
– Standard individual measurement: Upon each process call an individual
measurement can be executed by starting the conversion (waiting for its
end), by reading out the measurement values and if necessary by pro-
cessing them.
– Start of a burst measurement sequence: Upon each process call a com-
plete measurement sequence, which consists of a large number of indi-
vidual measurements, is started. The module executes the
measurement sequence alone, independent of the
ADwin system.
The measurement values - number and measurement frequency are to be
defined in the program - are stored in a special burst memory of the module,
which enables measurement frequencies of up to 2MHz. The size of the burst
memory limits the number of measurement values or the total time of the mea-
surement.
Only after end of the measurement sequence will you be able to read out the
stored measurement values from the burst memory and process them.
During an individual measurement the processor of the ADwin-Pro system is
checking the sequence of each individual measurement, whereas during a
burst measurement it is the module which is checking the measurement
sequence.
Fig. 122 – Pro-AIn-F-4/14 Rev. B : Block diagram
Input channels 4 differential
Resolution 14 bit
Conversion time max. 0.4µs (per ADC)
Sampling rate max. 2200ksps (per ADC)
Memory size 2
20
-1 = 1048575 measurement values total
Measurement ranges ±10V
Fig. 123 – Pro-AIn-F-4/14 Rev. B : Specification
AD
wi
n-
P
ro
bu
s
A
D
1
100k
100k
2
100k
100k
4
100k
100k
Addr.
Data
Buffer
+
-
A
D
Buffer
+
-
A
D
Buffer
+
-
A
D
Buffer
+
-
3
100k
100k
Data
Da
ta
A
dr
esse
PGA
G = 1, 2, 4, 8
+
-
PGA
G = 1, 2, 4, 8
+
-
PGA
G = 1, 2, 4, 8
+
-
Glue-
Logic
(Adress-Dekodierung,
Ablaufsteuerung,
SRAM-Steuerung)
SRAM
PGA
G = 1, 2, 4, 8
+
-