Jäger ADwin-Pro, System And Hardware Description

Page: 111 / 218

ADwin-Pro Hardware, manual version 2.9, June 2006
107
Pro I: Digital-I/O- and Counter Modules
Pro-CNT-VR4(-L)-I Rev. A
ADwin
Fig. 201 – Pro-CNT-VR4(-L)-I Rev. A Rev. A: Board and front panel
Fig. 199 – Pro-CNT-VR4-I Rev. A: Pin
assignment
Fig. 200 – Pro-CNT-VR4-L-I Rev. A:
Pin assignment
Counter 4 up/down counters
Counter resolution 32 bit
Input clock
rate edge evaluation 1.25MHz max. per channelA,B
clock, direction 10MHz max.
S i g n a l
pulse width edge evaluation min. 800ns per channelA,B
clock, direction min. 50ns
Event inputs 1
Input current typ. 7mA / max. 15mA
input voltage range
(selectable via jumpers)
0…5V 0 … 12V 0…24V
Switching threshold for 0-low 0…0.8V 0…1.6V 0…3.2V
Switching threshold for 1-high 4.5…5V 10…12V 20…24V
Input resistance 560
Ω
2 k
Ω
4.3 k
Ω
Input over-voltage -5V … 8V -5V … 16V -5V … 30V
Switching time 200ns
Connector 37-pin DSub socket
Isolation 42V channel-channel / channel-GND
Fig. 202 – Pro-CNT-VR4(-L)-I Rev. A : Specification
RESERVED
CNTR 1 (A / CLK) (-)
CNTR 1 (B / DIR) (-)
CNTR 1 CLR (-)
RESERVED
CNTR 2 (A / CLK) (-)
CNTR 2 (B / DIR) (-)
CNTR 2 CLR (-)
RESERVED
CNTR 3 (A / CLK) (-)
CNTR 3 (B / DIR) (-)
CNTR 3 CLK (-)
RESERVED
CNTR 4 (A / CLK) (-)
CNTR 4 (B / DIR) (-)
CNTR 4 CLR (-)
RESERVED
EVENT IN (+)
RESERVED
CNTR 1 (A / CLK) (+)
CNTR 1 (B / DIR) (+)
CNTR 1 CLR (+)
RESERVED
CNTR 2 (A / CLK) (+)
CNTR 2 (B / DIR) (+)
CNTR 2 CLR (+)
RESERVED
CNTR 3 (A / CLK) (+)
CNTR 3 (B / DIR) (+)
CNTR 3 CLR (+)
RESERVED
CNTR 4 (A / CLK) (+)
CNTR 4 (B / DIR) (+)
CNTR 4 CLR (+)
EVENT IN (-)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
RESERVED
RESERVED
CNTR 1, A (-)
CNTR 1, B (-)
CNTR 1, LATCH (-)
RESERVED
CNTR 2, A (-)
CNTR 2, B (-)
CNTR 2, LATCH (-)
RESERVED
CNTR 3, A (-)
CNTR 3, B (-)
CNTR 3, LATCH (-)
RESERVED
CNTR 4, A (-)
CNTR 4, B (-)
CNTR 4, LATCH (-)
RESERVED
EVENT IN (+)
RESERVED
CNTR 1, A (+)
CNTR 1, B (+)
CNTR 1, LATCH (+)
RESERVED
CNTR 2, A (+)
CNTR 2, B (+)
CNTR 2, LATCH (+)
RESERVED
CNTR 3, A (+)
CNTR 3, B (+)
CNTR 3, LATCH (+)
RESERVED
CNTR 4, A (+)
CNTR 4, B (+)
CNTR 4, LATCH (+)
EVENT IN (-)
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
RESERVED
19CNT01
ON
1 2 3 4 5 6 7 8
A0 A1 A2 A3 A4 A5 A6 A7
FPGA FPGA
74A
B
T
16245
74LS19
74LS19
74LS19
74LS19
74LS19
74LS19
74LS19
OCX
FPGA FPGA
FP
G
A
HCPL-2631 HCPL-2631 HCPL-2631
HCPL-2631
19CNTII1
HCPL-2631
+5
V
+
12V
+
24V
74LS19
HCPL-2631 HCPL-2631 HCPL-2631 HCPL-2631
+5
V
+
12V
+
24V +5
V
+
12V
+
24V +5
V
+
12V
+
24V +5
V
+
12V
+
24V +5
V
+
12V
+
24V +5
V
+
12V
+
24V +5
V
+
12V
+
24V +5
V
+
12V
+
24V
+5
V
+1
2
V
+2
4
V
+5
V
+1
2
V
+2
4
V
+5
V
+1
2
V
+2
4
V
+5
V
+1
2
V
+2
4
V
+5
V
+1
2
V
+2
4
V
+5
V
+1
2
V
+2
4
V
+5
V
+1
2
V
+2
4
V
+5
V
+1
2
V
+2
4
V
74LS19
74LS19
19/37 18/36 17/35 16/34 15/33 14/32 13/31 12/30
11/29 10/28 9/27 8/26 7/25 6/24 5/23 4/22
20/1
Sub-D-
Pin-Nr.:
Sub-D-
Pin-Nr.:
Sub-D-Pin-Nr.:
CNT-VR4-I
COUNTER
INPUT
CNT-VR4-L-I
COUNTER
INPUT