ADwin-Pro
Hardware, manual version 2.9, June 2006
129
Pro I: Digital-I/O- and Counter Modules
Pro-CO4-D Rev. A
ADwin
5.8.19 Pro-CO4-D Rev. A
The basic functions of the module
are similar to those of the
module
).
In addition, the module
is equipped with 2 decoders for the
connection of incremental encoders with SSI interface. All inputs are differen-
tial and can be used for RS422/485 levels (5V). Finally, the signalsA, B and
CLR are checked if they show short circuits or a cable break; you can obtain
this information with the instruction
CO4_GETSTATUS
.
It is possible to operate the EVENT input in differential mode as well as in sin-
gle-ended mode. If only a single-ended signal is available, it is to be set at
EVENT. The negative EVENT input is not set.
SSI decoder
An incremental encoder with SSI interface can be connected to one of the two
decoders. The signals are differential, too, and have RS422/485 levels.
The clock rates as well as the resolution of the encoder (up to 32 bits) are pro-
grammable via pre-scaler (of approx. 40kHz to 1MHz). A conversion from gray
into binary code is made by a routine to be programmed in the
ADbasic
pro-
cess (see below).
'PAR_1 = gray-value to be converted
'PAR_9 = result of the gray to binary conversion
DIMm, n AS LONG
EVENT:
IF(par_2=1) THEN 'start of conversion
m=0 'clear values of previous conv.
PAR_9=0 ' -"-
FOR n=1 TO 32 'go through all 32 bits
m=(SHIFT_RIGHT(PAR_1,(32-n)) AND 1) XORm
PAR_9=(SHIFT_LEFT(m,(32-n))) OR PAR_9
NEXT n
PAR_2=0 'enable next conversion
ENDIF
Fig. 248 – Listing: Conversion from gray code into binary code
Fig. 247 –
: Block diagram
NOTE:
Only counter #1 is shown for clarity of the schematic.
32 bit Counter
#1...#4
32 bit Latch
#5...#8
Control registers
32 bit Latch
#1...#4
CLK
EN
CLR
DIR
DIR
32 bit Latch
#9...#12
CO4_CLEAR
CO4_LATCHENABLE
CO4_CLEARENABLE
CO4_SETMODE
CNT_LATCH
CO4_SET_LATCHMODE
CO4_SETMODE
CO4_SET_LATCHMODE
G
40 MHz
CNT_ENABLE
ADw
in
-P
ro
bu
s
A/CLK/PWM
B/DIR
CLR/LATCH
32 bit SSI-decoder
#1, #2
A/CLK/PWM
B/DIR
CLR/LATCH
5V
12
0
10
k
10
k
10
k
12
0
120
120
EVENT
CLK
SDA
CLK
SDA
EVENT