Cypress PSoC CY8C23533, Technical Reference Manual

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220 Document # 001-20559 Rev. *D
Analog Interface
18.1.1 Analog Data Bus Interface
The Analog Data Bus Interface isolates the analog array and
analog system interface registers from the CPU system data
bus, to reduce bus loading. Transceivers are implemented
on the system data bus to isolate the analog data bus from
the system data bus. This creates a local analog data bus.
18.1.2 Analog Comparator Bus Interface
Each analog column has a dedicated comparator bus asso-
ciated with it. Every analog PSoC block has a comparator
output that can drive this bus. However, only one analog
block in a column can actively drive the comparator bus for a
column at any one time. The output on the comparator bus
drives into the digital blocks as a data input. It also serves as
an input to the decimator, as an interrupt input, and is avail-
able as read only data in the Analog Comparator Control
register (CMP_CR0).
Figure 18-1 illustrates one column of the comparator bus. In
the Continuous Time (CT) analog blocks, the CPhase and
CLatch bits of CT Block Control Register 2 determine
whether the output signal on the comparator bus is latched
inside the block, and if it is, which clock phase it is latched
on. In the Switched Capacitor (SC) analog blocks, the output
on the comparator bus is always latched. The ClockPhase
bit in SC Block Control Register 0 determines the phase on
which this data is latched and available.
The comparator bus is latched before it is available, to either
drive the digital blocks, interrupt, decimator, or for it to be
read in the CMP_CR0 register. The latch for each compara-
tor bus is transparent (the output tracks the input) during the
high period of PHI2. During the low period of PHI2, the latch
retains the value on the comparator bus during the high-to-
low transition of PHI2.
The CMP_CR0 register is described in the “CMP_CR0 Reg-
ister” on page 227 . There is also an option to force the latch
in each column into a transparent mode by setting bits in the
CMP_CR1 register.
As shown in Figure 18-1 , the comparator bus output is gated
by the primary output of a selected digital block. This feature
is used to precisely control the integration period of an incre-
mental ADC. Any digital block can be used to drive the gate
signal. This selection may be made with the ICLKS bits in
registers DEC_CR0 and DEC_CR1. This function may be
enabled on a column-by-column basis, by setting the IGEN
bits in the
DEC_CR0 register.
The analog comparator bus output values can be modified
or combined with another analog comparator bus through
the Analog
look-up table (LUT) function. The LUT takes
two inputs, A and B, and provides a selection of 16 possible
logic functions for those inputs. The LUT A and B inputs for
each column comparator output is shown in the following
table.
The LUT configuration is set in one control register,
ALT_CR0. Each selection for each column is encoded in
four bits. The function value corresponding to the bit encod-
ing is shown in the following table.
Table 18-1. A and B Inputs for Each Column Comparator
LUT Output
Comparator
LUT Output
A B
4 Column PSoCs
Column 0 ACMP0 ACMP1
Column 1 ACMP1 ACMP2
Column 2 ACMP2 ACMP3
Column 3 ACMP3 ACMP0
2 Column PSoCs
Column 0 ACMP0 ACMP1
Column 1 ACMP1 0
Column 2 0 0
Column 3 0 ACMP0
1 Column PSoCs
Column 0 ACMP0 0
Column 1 0 0
Column 2 0 0
Column 3 0 ACMP0
Table 18-2. RDIxLTx Register
LUTx[3:0] 0h: 0000: FALSE
1h: 0001: A .AND. B
2h: 0010: A .AND. B
3h: 0011: A
4h: 0100: A .AND. B
5h: 0101: B
6h: 0110: A .XOR. B
7h: 0111: A .OR. B
8h: 1000: A .NOR. B
9h: 1001: A .XNOR. B
Ah: 1010: B
Bh: 1011: A .OR. B
Ch: 1100: A
Dh: 1101: A .OR. B
Eh: 1110: A. NAND. B
Fh: 1111: TRUE