Cypress PSoC CY8C23533, Technical Reference Manual

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182 Document # 001-20559 Rev. *D
Digital Blocks
Figure 17-4. CRCPRS LFSR Structure
LSFR Structure
The LSFR (Linear Feedback Shift register) structure, as
shown in
Figure 17-4 , is implemented as a modular shift
register generator. The least significant block in the chain
inputs the MSb and XORs it with the DATA input, in the case
of CRC computation. For PRS computation, the DATA input
is forced to logic 0 (by input selection); and therefore, the
MSb bus is directly connected to the FB bus. In the case of
a chained block, the data input (DIN) comes directly from
the data output (DO) of the LFSR in the previous block. The
MSb selection, derived from the priority decode of the poly-
nomial, enables one of the tri-state drivers to drive the MSb
bus.
Determining the CRC Polynomial
Computation of an n-bit result is generally specified by a
polynomial with n+1 terms, the last of which is X
16
, where
Equation 1
As an example, the CRC-CCIT 16-bit polynomial is:
Equation 2
The CRCPRS hardware assumes the presence of the X
0
term; and therefore, this polynomial can be expressed in 16
bits as 1000100000010000 or 8810h. Two consecutive digi-
tal blocks may be allocated to perform this function, with 88h
as the MS block polynomial (DR1) and 10h as the LS block
polynomial value.
Determining the PRS Polynomial
Generally, PRS polynomials are selected from pre-com-
puted reference tables. It is important to note that there are
two common ways to specify a PRS polynomial: simple reg-
ister configuration and modular configuration. In the simple
method, a
shift register is implemented with a reduction
XOR of the MSb and feedback taps as input into the least
significant bit.
In the modular method, there is an XOR operation imple-
mented between each register bit and each tap point
enables the XOR with the MSb for that given bit. The
CRCPRS function implements the modular approach.
These are equivalent methods. However, there is a conver-
sion that should be understood. If tables are specified in
simple register format, then a conversion can be made to
the modular format by subtracting each tap from the MS tap,
as shown in the following example.
To implement a 7-bit PRS of length 127, one possible code
is [7,6,4,2]s, which is in simple format. The modular format
is [7,7-6,7-4,7-2]m or [7,1,3,5]m which is equivalent to [7, 5,
3, 1]. Determining the polynomial to program is similar to the
CRC example above. Set a
binary bit for each tap (with bit 0
of the register corresponding to tap 1). Therefore, the code
[7,5,3,1] corresponds to 01010101 or 55h.
In both the CRC and PRS cases, an appropriate seed value
should be selected. All ones for PRS, or all ones or all zeros
for CRC are typical values. Note that a seed value of all
zeros should not be used in a PRS function, because PRS
counting is inhibited by this seed.
17.1.9.1 Usability Exceptions
Following is a usability exception for the CRCPRS function.
1. The polynomial register must only be written when the
block is disabled.
17.1.9.2 Block Interrupt
The CRCPRS block has one fixed interrupt source, which is
the compare auxiliary output.
DO
0 1 2 7 6
FB Tri-State Bus
DATA
MSB Tri-State Bus
PO
L
Y
[0
]
PO
L
Y
[1
]
PO
L
Y
[6
]
PO
L
Y
[7
]
2:1
DIN
(From previous block
DO, if chained.)
(Data input for CRC, if
PRS, force to logic ‘0’.)
(To next block,
if chained.)
MSB SEL is determined by a
priority decode of the MSB, of
the polynomial across all blocks
of a CRCPRS function.
MSB
SEL
X
0
1 =
CRC CCIT – X
16
X
12
X
5
1 + + + =