Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 189
Digital Blocks
17.2.1.2 Counter Register Definitions
There are three 8-bit Data registers and a 2-bit Control register. Table 17-6 explains the meaning of these registers in the con-
text of the counter operation. Note that the descriptions of the registers are dependent on the enable/disable state of the
block. This behavior is only related to the enable bit in the Control register, not the data input that provides the counter gate
(unless otherwise noted).
Note DR0 may only be read (to transfer DR0 data to DR2) when the block is disabled.
17.2.1.3 Dead Band Register Definitions
There are three 8-bit Data registers and a 3-bit Control register. Table 17-7 explains the meaning of these registers in the con-
text of dead band operation.
Note DR0 may only be read (to transfer DR0 data to DR2) when the block is disabled.
Table 17-6. Counter Data Register Descriptions
Name Function Description
DR0 Count Value Not directly readable or writeable.
During normal operation, DR0 stores the current count of a synchronous down counter.
When disabled, a write to the DR1 period register is also simultaneously loaded into DR0 from the data bus.
When disabled or the data input (counter gate) is low, a read of DR0 returns 00h to the data bus and transfers the contents
of DR0 to DR2. This register should not be read when the counter is enabled and counting.
DR1 Period Write only register.
Data in this register sets the period of the count. The actual number of clocks counted is 1.
A period of 00h gives a constant logic high on the auxiliary output.
When disabled, a write to this register also transfers the period value directly into DR0.
When enabled, if the block frequency is 24 MHz or below, this register may be written to at any time, but the period is only
reloaded into DR0 in the clock following a TC. If the block frequency is 48 MHz, the terminal count or compare interrupt
should be used to synchronize the new period register write; otherwise, the counter could be incorrectly loaded.
DR2 Compare Read write register.
DR2 functions as a compare register.
When enabled, the compare output is computed using the compare type (set in the function register mode bits) between
DR0 and DR2. The result of the compare is output to the primary output.
When disabled or the data input (counter gate) is low, a read of DR0 transfers the contents of DR0 into DR2.
DR2 may be written to when the function is enabled or disabled.
Table 17-7. Dead Band Register Descriptions
Name Function Description
DR0 Count Value Not directly readable or writeable.
During normal operation, DR0 stores the current count of a synchronous down counter.
When disabled, a write to the DR1 period register is also simultaneously loaded into DR0 from the data bus.
When disabled, a read of DR0 returns 00h to the data bus and transfers the contents of DR0 to DR2.
DR1 Period Write only register.
Data in this register sets the period of the dead band count. The actual number of clocks counted is 1. The mini-
mum period value is 00h, which sets a dead band time of one clock.
When disabled, a write to this register also transfers the period value directly into DR0.
When enabled, if the block frequency is 24 MHz or below, this register may be written to at any time, but the period is only
reloaded into DR0 in the clock following a terminal count (TC). If the block frequency is 48 MHz, the terminal count or com-
pare interrupt should be used to synchronize the new period register write; otherwise, the counter could be incorrectly
loaded.
DR2 Buffer When disabled, a read of DR0 transfers the contents of DR0 into DR2.