Cypress PSoC CY8C23533, Technical Reference Manual

Page: 289 / 410

Document # 001-20559 Rev. *D 225
Analog Interface
To represent the true sign of the input voltage, you must invert the sign of the result from the DAC register. Therefore, the
result becomes Sign = 0, Magnitude = 12, which is (3.75 – 2.5)/32 * 12 + 2.5 = 2.96875. The error is 31.25 mV, or less that
one LSb of 39 mV.
Notes
1. VSum is the voltage at the summing node, that is, the input to the comparator.
2. VDac is the voltage generated by the DAC block from the ACap value.
3. When VSum > AGND, CMP = 0; when VSum < AGND, CMP = 1.
4. CMP = 0 means keep the bit (undershoot); CMP = 1 means clear the bit (overshoot).
5. Start with Sign = 1 (configuration programming), equivalent to setting that bit to test.
As shown in Table 18-4 , the value of the result from Step 5,
Magnitude = 13, is closer to the actual value of 12.8. This
demonstrates that even though it is possible that the result-
ing code could be closer to the actual value, in the SAR
algorithm there is no provision to detect this. The result is a
maximum theoretical error of less than one LSb.
Implementing Higher Resolution SARs
It is straightforward to implement higher resolution SARs
using the SAR hardware accelerator. For example, to create
an 11-bit SAR, 3 blocks are allocated: 2 SC blocks to make
a DAC9 and one SC or CT block for summing and compare.
To get the results of the most significant (MS) block, which is
the first 6 bits (Sign and 5 bits of Magnitude), the firmware
sequencing proceeds exactly as in the previous SAR6
example.
The trick with the least significant (LS) block of the DAC9 is
to get the sign right. For the output to be correct, the sign of
the LS block of a DAC9 should be opposite to that of the MS
block (since it is connected through an inverting input to the
MS block).
There are two possible ways to handle this.
1. In firmware, one can manually compute what the SIGN
bit should be from the result in the MS block and write it
to the LS block. Then the SAR count value should be set
to 5 instead of 6 to skip the sign bit check.
2. An interesting property of the SAR algorithm is that the
resulting voltage at the summing node after the first 6
steps (MS block processing) is going to be the same
polarity (above or below AGND) as the input voltage.
The reason for this is that, by definition, if the polarity of
the summing voltage is opposite to that of the input volt-
age, this triggers a clear of the previous bit set. Since,
also by definition, the final result of the summing voltage
is less than one LSb from AGND, clearing the LSb
results in a summing voltage of the same polarity as the
input voltage.
According to number 2 above, the sign bit of the LS block
can be handled exactly as the SIGN bit of the MS block, just
another OR instruction. This sequence is then appended on
the above MS processing sequence (substituting the LS
DAC block address for <LS_CR0>). Note that the meaning
of the comparator is inverted by setting the SIGN bit in the
ASYNC Control register. This is because the LS block is
inverted with respect to the MS block.
mov reg[ASY_CR], 68h // SAR count value=6,
// Sign=1, Col=0
or reg[<LS_CR0>], 0 // Check sign, set bit 4
or reg[<LS_CR0>], 0 // Check bit 4, set bit 3
or reg[<LS_CR0>], 0 // Check bit 3, set bit 2
or reg[<LS_CR0>], 0 // Check bit 2, set bit 1
or reg[<LS_CR0>], 0 // Check bit 1, set bit 0
or reg[<LS_CR0>], 0 // Check bit 0
Table 18-4. SAR Sequence Example
Step Current ACap VIn VDac VSum
Comparator
Bus (CMP)
New ACap Comment
1 100000 3.0 2.5 2.75 0 110000 Keep the sign bit and set bit 4.
2 110000 3.0 1.875 2.4375 1 101000 Overshoot , clear bit 4, set bit 3.
3 101000 3.0 2.1875 2.59375 0 101100 Keep bit 3, and set bit 2.
4 101100 3.0 2.03125 2.515625 0 101110 Keep bit 2, and set bit 1.
5 101110 3.0 1.953125 2.4765625 1 101101 Overshoot , clear bit 1, set bit 0.
6 101101 3.0 1.992188 2.496094 1 101100 Overshoot , clear bit 0
101100 3.0 2.03125 2.515625 0 101100 Final Result