Document # 001-20559 Rev. *D
207
Digital Blocks
Figure 17-21. Typical SPIS Timing in Modes 2 and 3
Slave Select (SS_, active low).
Slave Select must be
asserted to enable the SPIS for receive and transmit. There
are two ways to do this:
1. Drive the auxiliary input from a pin (selected by the Aux
IO Select bits in the output register). This gives the SPI
master control of the slave selection in a multi-slave
environment.
2. SS_ may be controlled in firmware with register writes to
the output register. When Aux IO Enable = 1, Aux IO
Select bit 0 becomes the SS_ input. This allows the user
to save an input pin in single-slave environments.
When SS_ is negated (whether from an external or internal
source), the SPIS state machine is reset and the MISO out-
put is forced to idle at logic 1. In addition, the SPIS ignores
any incoming MOSI/SCLK input from the master.
Status Generation and Interrupts.
There are four status
bits in the SPIS Block: TX Reg Empty, RX Reg Full, SPI
Complete, and Overrun. The timing of these status bits is
identical to the SPIM, with the exception of TX Reg Empty,
which is covered in the section on TX data queuing.
Status Clear On Read.
Refer to the same subsection in
.
TX Data Queuing.
Most SPI applications call for data to be
sent back from the slave to the master. Writing firmware to
accomplish this requires an understanding of how the shift
register is loaded from the TX Buffer register.
All modes use the following mechanism: 1) If there is no
transfer in progress, 2) if the shifter is empty, and 3) if data is
available in the TX Buffer register, the byte is loaded into the
shifter.
The only difference between the modes is that the definition
of “transfer in progress” is slightly different between modes 0
and 1, and modes 2 and 3.
illustrates TX data loading in modes 0 and 1. A
transfer in progress is defined to be from the falling edge of
SS_ to the point at which the RX Buffer register is loaded
with the received byte. This means that in order to send a
byte in the next transfer, it must be loaded into the TX Buffer
register before the falling edge of SS_. This ensures a mini-
mum set up time for the first bit, since the leading edge of
the first SCLK must latch in the received data. If SS_ is not
toggled between each byte or is forced low through the con-
figuration register, the leading edge of SCLK is used to
define the start of transfer. However, in this case, the user
must provide the required set up time (one-half clock mini-
mum before the leading edge), with a knowledge of system
latencies and response times.
SCLK (Internal)
TX REG EMPTY
D7
MISO
D6
D5
D2
D1
D0
D7
User writes the first
byte to the TX Buffer
register.
Shifter is loaded with
first byte (by leading
edge of the SCLK).
User writes the next
byte to the TX Buffer
register.
SCLK (MODE 2)
Shifter is
loaded with
the next byte.
Last bit of received data is valid
on this edge and is latched into
the RX Buffer register.
SCLK (MODE 3)
RX REG FULL
First
input bit
latched.
First
Shift
Summary of Contents for PSoC CY8C23533
Page 4: ...Contents Overview 4 Document 001 20559 Rev D Section G Glossary 385 Index 401 ...
Page 16: ...Contents Overview 16 Document 001 20559 Rev D ...
Page 24: ...24 Document 001 20559 Rev D Section A Overview ...
Page 30: ...30 Document 001 20559 Rev D Pin Information ...
Page 54: ...54 Document 001 20559 Rev D Supervisory ROM SROM ...
Page 60: ...60 Document 001 20559 Rev D RAM Paging ...
Page 68: ...68 Document 001 20559 Rev D Interrupt Controller ...
Page 76: ...12 Document 001 20559 Rev D General Purpose IO GPIO ...
Page 82: ...18 Document 001 20559 Rev D Internal Main Oscillator IMO ...
Page 84: ...20 Document 001 20559 Rev D Internal Low Speed Oscillator ILO ...
Page 90: ...26 Document 001 20559 Rev D External Crystal Oscillator ECO ...
Page 94: ...30 Document 001 20559 Rev D Phase Locked Loop PLL ...
Page 106: ...42 Document 001 20559 Rev D Sleep and Watchdog ...
Page 228: ...164 Document 001 20559 Rev D Section D Digital System ...
Page 234: ...170 Document 001 20559 Rev D Array Digital Interconnect ADI ...
Page 278: ...214 Document 001 20559 Rev D Digital Blocks ...
Page 296: ...232 Document 001 20559 Rev D Analog Interface ...
Page 304: ...240 Document 001 20559 Rev D Analog Array ...
Page 308: ...244 Document 001 20559 Rev D Analog Input Configuration ...
Page 312: ...248 Document 001 20559 Rev D Analog Reference ...
Page 338: ...274 Document 001 20559 Rev D Section F System Resources ...
Page 354: ...290 Document 001 20559 Rev D Multiply Accumulate MAC ...
Page 374: ...310 Document 001 20559 Rev D I2C ...
Page 400: ...336 Document 001 20559 Rev D Section G Glossary ...