Document # 001-20559 Rev. *D
47
Supervisory ROM (SROM)
Address F8h is the return code byte for all SROM functions
(except Checksum and TableRead); for this function, the
only acceptable values are 00h and 02h. Address FCh is the
fail count variable. After POR (Power on Reset) or WDR, or
XRES (External Reset), the variable is initialized to 00h by
the SROM. Each time the checksum fails, the fail count is
incremented. Therefore, if it takes two passes through
SWBootReset to get a good checksum, the fail count would
be 01h.
3.1.2.2
ReadBlock Function
The ReadBlock function is used to read 64 contiguous bytes
from Flash: a
. The number of blocks in a device is the
total number of bytes divided by 64. Refer to
determine the amount of space in your PSoC device.
The first thing the ReadBlock function does is check the pro-
tection bits to determine if the desired BLOCKID is readable.
If read protection is turned on, the ReadBlock function exits
setting the accumulator and KEY2 back to 00h. KEY1 has a
value of 01h, indicating a read failure.
If read protection is not enabled, the function reads 64 bytes
from the Flash using a ROMX instruction and stores the
results in SRAM using an MVI instruction. The 64 bytes are
stored in SRAM, beginning at the address indicated by the
value of the POINTER parameter. When the ReadBlock
completes successfully, the accumulator, KEY1, and KEY2
all have a value of 00h.
If the PSoC device has more than one bank of Flash, the
bank value in the FLS_PR1 register must be set prior to
executing the SSC instruction. Refer to
.
Note
MVI [expr], A is used to store the Flash
block contents
in SRAM; thus, the MVW_PP register can be set to indicate
which SRAM pages receive the data.
Table 3-4. SRAM Map Post SWBootReset (00h)
Address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0x0_
0x00
0x00
0x00
??
??
??
??
??
??
??
??
??
??
??
??
??
0x1_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0x2_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0x3_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0x4_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0x5_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0x6_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0x7_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0x8_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0x9_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0xA_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0xB_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0xC_
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
??
0xD_
??
??
??
??
??
??
??
??
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE_
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xF_
0x00
0x00
0x00
0x00
0x00
0x00
??
??
0x00
0x02
xx
0x00
0x00
0xn
xx
0x00
0x00
Table 3-5. Flash Memory Organization
PSoC Device
Amount of
Flash
Amount of
SRAM
Number of
Blocks
per Bank
Number of
Banks
CY8C24633
8 KB
256 Bytes
128
2
CY8C23433
8 KB
256 Bytes
128
2
CY8C23533
8 KB
256 Bytes
128
2
CY8C24533
8 KB
256 Bytes
128
2
CY8C24x23A
4 KB
256 Bytes
64
1
Table 3-6. ReadBlock Parameters (01h)
Name
Address
Type
Description
MVW_PP
0,D5h
Register
MVI write page pointer register.
KEY1
0,F8h
RAM
3Ah.
KEY2
0,F9h
RAM
Stack Pointer value+3, when SSC is
executed.
BLOCKID
0,FAh
RAM
Flash block number.
POINTER
0,FBh
RAM
Addresses in SRAM where returned
data should be stored.
FLS_PR1
1,FAh
Register
Flash bank number.
Summary of Contents for PSoC CY8C23533
Page 4: ...Contents Overview 4 Document 001 20559 Rev D Section G Glossary 385 Index 401 ...
Page 16: ...Contents Overview 16 Document 001 20559 Rev D ...
Page 24: ...24 Document 001 20559 Rev D Section A Overview ...
Page 30: ...30 Document 001 20559 Rev D Pin Information ...
Page 54: ...54 Document 001 20559 Rev D Supervisory ROM SROM ...
Page 60: ...60 Document 001 20559 Rev D RAM Paging ...
Page 68: ...68 Document 001 20559 Rev D Interrupt Controller ...
Page 76: ...12 Document 001 20559 Rev D General Purpose IO GPIO ...
Page 82: ...18 Document 001 20559 Rev D Internal Main Oscillator IMO ...
Page 84: ...20 Document 001 20559 Rev D Internal Low Speed Oscillator ILO ...
Page 90: ...26 Document 001 20559 Rev D External Crystal Oscillator ECO ...
Page 94: ...30 Document 001 20559 Rev D Phase Locked Loop PLL ...
Page 106: ...42 Document 001 20559 Rev D Sleep and Watchdog ...
Page 228: ...164 Document 001 20559 Rev D Section D Digital System ...
Page 234: ...170 Document 001 20559 Rev D Array Digital Interconnect ADI ...
Page 278: ...214 Document 001 20559 Rev D Digital Blocks ...
Page 296: ...232 Document 001 20559 Rev D Analog Interface ...
Page 304: ...240 Document 001 20559 Rev D Analog Array ...
Page 308: ...244 Document 001 20559 Rev D Analog Input Configuration ...
Page 312: ...248 Document 001 20559 Rev D Analog Reference ...
Page 338: ...274 Document 001 20559 Rev D Section F System Resources ...
Page 354: ...290 Document 001 20559 Rev D Multiply Accumulate MAC ...
Page 374: ...310 Document 001 20559 Rev D I2C ...
Page 400: ...336 Document 001 20559 Rev D Section G Glossary ...