Cypress PSoC CY8C23533, Technical Reference Manual

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212 Document # 001-20559 Rev. *D
Digital Blocks
As shown in Figure 17-28 , the internal bit clock (CCLK) runs slower than the external TX bit clock and the STOP bit is sam-
pled later than the actual center point. After the STOP bit is sampled, the 24 MHz reset pulse forces the receiver back to an
idle state. In this state, the next START bit search is initiated, resynchronizing the RX bit clock to the TX bit clock.
Figure 17-28. Clock Generation and Start Detection
This resynchronization process (forcing the state back to
idle) occurs regardless of the value of the STOP bit sample.
It is important to reset as soon as possible, so that maximum
performance can be achieved.
Figure 17-29 shows an
example where the RX block clock bit rate is slower than the
external TX bit rate. The sample point shifts to successively
later times. In the extreme case shown, the RX samples the
STOP bit at the trailing edge. In this case, the receiver
counts 9.5 bit times, while the transmitter counts 10 bit
times. Therefore, for a 10-bit message, the maximum theo-
retical clock offset, for the message to be received correctly,
is represented by one-half bit time or five percent. If the RX
and TX clocks exceed this offset, a logic 0 may be sampled
for the STOP bit. In this case, the Framing Error status is
set.
Figure 17-29. Example RX Re-Synchronization
This theoretical maximum is degraded by the resynchroniza-
tion time, which is fixed at approximately 42 ns. In a typical
115.2 Kbaud example, the bit time is 8.70

s. In this case
the new maximum offset is:
((4.35 ms - 42 ns) / 4.35 ms) x 5% or 4.95%
At slower baud rates, this value gets closer to the theoretical
maximum of five percent.
Status Generation. There are five status bits in a receiver
block: RX Reg Full, RX Active, Framing Error, Overrun, and
Parity Error. All status bits, except RX Active and Overrun,
are set synchronously on the STOP bit sample point.
RX Reg Full indicates a byte has been received and trans-
ferred into the RX Buffer register. This status bit is cleared
when the user reads the RX Buffer register (DR2). The set-
ting of this bit is synchronized to the STOP sample point.
This is the earliest point at which the Framing Error status
can be set; and therefore, error status is defined to be valid
when RX Reg Full is set.
RX Active can be polled to determine if a reception is in
progress. This bit is set on START detection and cleared on
STOP detection. This bit is not
sticky and there is no way
for the user to clear it.
CLKIN
RXD
(ASYNCH)
START STATE
Input is sampled at the
center of the bit time.
Start detection enables
the clock divider.
CCLK
RESET
(CLK GEN)
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0
COUNT
IDLE BIT0
1
BIT0 START BIT
0 1 2 3 7 0 1
Actual
center of
STOP bit.
STOP bit
sample
point.
Width of reset is
one 24 MHz
clock pulse.
Next
START bit.
RXACTIVE
START is confirmed with
another sample at the
3rd sample clock.
STOP
IDLE
STOP
Reset to IDLE
and initiate
search for a new
START bit.
Start
1 1 0 1 0 0 1 0 1
RXD
Stop Start
RX clock is slower than TX clock.
Stop bit is just
recognized.
Need to re-sync
as soon as
possible.
Any delay in
re-sync cuts
into optimal
sync of the next
byte.
Sample points are
successively later
in the bit times.