Document # 001-20559 Rev. *D
81
x,86h
13.2.31
ASDxxCR2
Analog Switch Cap Type D Block Control Register 2
This register is one of four registers used to configure a type D switched capacitor PSoC block.
The register naming convention for arrays of PSoC blocks and their registers is <Prefix>mn<Suffix>, where m=row index,
n=column index; therefore, ASD11CR2 is a register for an analog PSoC block in row 1 column 1. For additional information,
refer to the
“Register Definitions” on page 258
in the Switched Capacitor Block chapter.
7
AnalogBus
Enable output to the analog bus. Note that ClockPhase in ASDxxCR0 register, bit 6, also effects this
bit: Hold mode is allowed only if ClockPhase = 0.
0
Disable output to analog column bus.
1
Enable output to analog column bus.
6
CompBus
Enable output to the comparator bus.
0
Disable output to comparator bus.
1
Enable output to comparator bus.
5
AutoZero
Bit for controlling the AutoZero switch.
0
Shorting switch is not active. Input cap branches shorted to opamp input.
1
Shorting switch is enabled during Internal PHI1. Input cap branches shorted to analog
ground during Internal PHI1 and to opamp input during Internal PHI2.
4:0
CCap[4:0]
Binary encoding for 32 possible capacitor sizes for capacitor CCap.
Individual Register Names and Addresses:
x,86h
ASD11CR2 : x,86h
7
6
5
4
3
2
1
0
Access : POR
RW : 0
RW : 0
RW : 0
RW : 00
Bit Name
AnalogBus
CompBus
AutoZero
CCap[4:0]
Bits
Name
Description
Summary of Contents for PSoC CY8C23533
Page 4: ...Contents Overview 4 Document 001 20559 Rev D Section G Glossary 385 Index 401 ...
Page 16: ...Contents Overview 16 Document 001 20559 Rev D ...
Page 24: ...24 Document 001 20559 Rev D Section A Overview ...
Page 30: ...30 Document 001 20559 Rev D Pin Information ...
Page 54: ...54 Document 001 20559 Rev D Supervisory ROM SROM ...
Page 60: ...60 Document 001 20559 Rev D RAM Paging ...
Page 68: ...68 Document 001 20559 Rev D Interrupt Controller ...
Page 76: ...12 Document 001 20559 Rev D General Purpose IO GPIO ...
Page 82: ...18 Document 001 20559 Rev D Internal Main Oscillator IMO ...
Page 84: ...20 Document 001 20559 Rev D Internal Low Speed Oscillator ILO ...
Page 90: ...26 Document 001 20559 Rev D External Crystal Oscillator ECO ...
Page 94: ...30 Document 001 20559 Rev D Phase Locked Loop PLL ...
Page 106: ...42 Document 001 20559 Rev D Sleep and Watchdog ...
Page 228: ...164 Document 001 20559 Rev D Section D Digital System ...
Page 234: ...170 Document 001 20559 Rev D Array Digital Interconnect ADI ...
Page 278: ...214 Document 001 20559 Rev D Digital Blocks ...
Page 296: ...232 Document 001 20559 Rev D Analog Interface ...
Page 304: ...240 Document 001 20559 Rev D Analog Array ...
Page 308: ...244 Document 001 20559 Rev D Analog Input Configuration ...
Page 312: ...248 Document 001 20559 Rev D Analog Reference ...
Page 338: ...274 Document 001 20559 Rev D Section F System Resources ...
Page 354: ...290 Document 001 20559 Rev D Multiply Accumulate MAC ...
Page 374: ...310 Document 001 20559 Rev D I2C ...
Page 400: ...336 Document 001 20559 Rev D Section G Glossary ...