Cypress PSoC CY8C23533, Technical Reference Manual

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180 Document # 001-20559 Rev. *D
Digital Blocks
17.1.7 Counter Function
A counter consists of a period register, a synchronous down
counter, and a compare register. The counter function is
identical to the timer function except for the following points:
■ The data input is a counter gate (enable), rather than a
capture input. Counters do not implement synchronous
capture. The DR0 register in a counter should not be
read when it is enabled.
■ The compare output is the primary output and the termi-
nal count (TC) is the auxiliary output (opposite of the
timer).
■ Terminal count output is full cycle only.
When the counter is disabled and a period value is written
into DR1, the period value is also loaded into DR0. When
the counter is enabled, the counter counts down until termi-
nal count (a count of 00h) is reached. On the next clock
edge, the period is reloaded and, on subsequent clocks,
counting continues. (Refer to the timing diagram for this
function on page
199 .)
The counter implements a compare function between DR0
and DR2. The compare signal is the primary function output.
Mode bit 1 sets the compare type (DR0 <= DR2 or DR0 <
DR2) and Mode bit 0 sets the interrupt type (terminal count
or compare).
The data input functions as a gate to counter operation. The
counter only counts and reloads when the data input is
asserted (logic 1). When the data input is negated (logic 0),
counting (including the period reload) is halted.
Counters may be chained in 8-bit blocks up to 32 bits.
17.1.7.1 Usability Exceptions
The following is a usability exception for the counter func-
tion.
1. DR0 may only be read (to transfer DR0 data to DR2)
when the block is disabled.
17.1.7.2 Block Interrupt
The counter block has a selection of two interrupt sources.
interrupt on terminal count (TC) and interrupt on compare
may be selected in Mode bit 0 of the function register.
■ Interrupt on Terminal Count : The positive edge of ter-
minal count (auxiliary output) generates an interrupt for
this block. The timing of the interrupt follows the TC
pulse width setting in the control register.
■ Interrupt on Compare : The positive edge of compare
(primary output) generates an interrupt for this block.
17.1.8 Dead Band Function
The dead band function generates output signals on both
the primary and auxiliary outputs of the block, see
Figure 17-3 . Each of these outputs is one phase of a two-
phase, non-overlapping clock generated by this function.
The two clock phases are never high at the same time and
the period between the clock phases is known as the
dead
band . The width of the dead band time is determined by the
value in the period register. This dead band function can be
driven with a PWM as an input clock or it can be clocked
directly by toggling a bit in software using the Bit Bang inter-
face. If the clock source is a PWM, this makes a two output
PWM with guaranteed non-overlapping outputs. An active
asynchronous signal on the KILL data input disables both
outputs immediately.
The PWM with the Dead Band User Module configures one
or two blocks to create an 8- or 16-bit PWM and configures
an additional block as the dead band function.
A dead band consists of a period register, a synchronous
down counter, and a special dead band circuit. The DR2
register is only used to read the contents of DR0. As with the
counter, when the dead band is disabled and a period value
is written into DR1, the period value is also loaded into DR0.
(Refer to the timing diagrams for this function on page
200 .)
Figure 17-3. Dead Band Functional Overview
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Primary Output
Auxiliary
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Dead
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