Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 223
Analog Interface
18.3.1.1 Architectural Description
The architectural description for the SAR hardware accelerator is illustrated in Figure 18-5 .
Figure 18-5. SAR Hardware Accelerator
As shown in Figure 18-5 , the SAR accelerator hardware is
interfaced to the analog array through the comparator output
and the analog array data bus. To create DAC output, val-
ues are written directly to the ACAP field in the DAC regis-
ter. To facilitate the sequencing of the DAC writes in the SAR
algorithm, the M8C is programmed to do a sequence of
READ, MODIFY, and WRITE instructions. This is an atomic
operation that consists of an IO read (IOR) followed closely
by an IO write (IOW). One example of an assembly level
instruction is as follows.
OR reg[DAC_REG],0
The effect of this instruction is to read the DAC register and
follow it closely in time by a write back. The OR instruction
does not modify the read data (it is OR’ed with ‘0’). The CPU
does not need to do any additional computation in conjunc-
tion with this procedure. The SAR hardware transparently
does the data modification during the read portion of the
cycle. The only purpose for executing this instruction is to
initiate a read that is modified by the SAR hardware, then to
follow up with a write that transfers the data back to the DAC
register.
During each IO read operation, the SAR hardware overrides
two bits of the data:
■
To correct the previous bit guess based on the current
comparator value.
■
To set the next guess (next least significant bit).
The CPU latches this SAR modified data, OR’s it with ‘0’ (no
CPU modification), and writes it back to the DAC register. A
counter in the SAR hardware is used to decode which bits
are being operated on in each cycle. In this way, the capabil-
ity of the CPU and the IOR/IOW control lines are used to
implement the read and write.
Use the SAR accelerator hardware to make the decisions
and to control the values written, achieving the optimal level
of performance for the current system.
The SAR hardware is designed to process six bits of a result
in a given sequence. A higher resolution SAR is imple-
mented with multiple passes.
18.3.1.2 Application Description
There are a number of ways to map a SAR6 module into the
analog array. A SAR6 can be created from 1 SC block, 2 SC
blocks, or 1 SC block and 1 CT block. In the following exam-
ple, the programming, the clock selection, connectivity,
inputs, of a two block SAR6 is demonstrated.
This type of SAR6 is made up of 1 SC block that operates
as a DAC6, and 1 SC block that operates as a voltage sum-
mer and comparator. The 2 block SAR6 is placed in column
1 as shown in
Figure 18-6 .
Figure 18-6. SAR6 Module Example
DAC Register
Analog Data Bus
Analog
Input
System
Data Bus
SAR
Accelerator
M8C
Micro
DAC
CMP
Latch
CBUS
Driver
PHI1 or PHI2
SAR Accelerator
Input Mux
Comparator
Bus Outputs
from Other
Columns
Switched Capacitor Block
DB
Read
ASD11
(DAC6)
ASC21
(CMP)
Port 2[3]
CM
P
B
U
S