Cypress PSoC CY8C23533, Technical Reference Manual

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176 Document # 001-20559 Rev. *D
Row Digital Interconnect (RDI)
16.2.5 RDIxROx Registers
The Row Digital Interconnect Row Output Register 0 and 1
(RDIxRO0 and RDIxRO1) are used to select the global nets
that the row outputs drive.
The final configuration bits for outputs from digital PSoC
rows are in the two RDIxROx registers. These registers hold
the 16 bits that can individually enable the tri-state buffers
that connect to all eight of the Global Output Even lines and
all eight of the Global Output Odd lines to the row LUTs.
The input to these tri-state drivers are the outputs of the
row’s LUTs, as shown in
Figure 16-2 . This means that any
row can drive any global output.
16.2.5.1 RDIxRO0 Register
Bits 7 to 4: GOxxEN. These configuration bits enable the
tri-state buffers that connect to the Global Output Even lines
for LUT 1.
Bits 3 to 0: GOxxEN. These configuration bits enable the
tri-state buffers that connect to the Global Output Even lines
for LUT 0.
For additional information, refer to the RDIxRO0 register on
page 92 .
16.2.5.2 RDIxRO1 Register
Bits 7 to 4: GOxxEN. These configuration bits enable the
tri-state buffers that connect to the Global Output Even lines
for LUT 3.
Bits 3 to 0: GOxxEN. These configuration bits enable the
tri-state buffers that connect to the Global Output Even lines
for LUT 2.
For additional information, refer to the RDIxRO1 register on
page 93 .
16.3 Timing Diagram
Figure 16-4. Optional Row Input Sync. to SYSCLK
Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
x,B5h RDI0RO0 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW : 00
x,B6h RDI0RO1 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW : 00
LEGEND
x An “x” before the comma in the address field indicates that the register exists in both register banks.
SYSCLK
GLOBAL INPUT
ROW INPUT
Set up to positive edge.
Output of the synchronizer changes on the second
positive edge that follows the input transition.