Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 305
I2C
28.4.3 Status Timing
Figure 28-6 illustrates the interrupt timing for Byte Com-
plete, which occurs on the positive edge of the ninth clock
(byte + ACK/NACK) in transmit mode and on the positive
edge of the eighth clock in receive mode. There is a maxi-
mum of three cycles of latency, due to the input synchro-
nizer/filter circuit. As shown, the interrupt occurs on the
clock following a valid SCL positive edge input transition
(after the synchronizers). The Address bit is set with the
same timing, but only after a slave address has been
received. The LRB (Last Received Bit) status is also set with
the same timing, but only on the ninth bit after a transmitted
byte.
Figure 28-6. Byte Complete, Address, LRB Timing
Figure 28-7 shows the timing for Stop Status. This bit is set
(and the interrupt occurs) two clocks after the synchronized
and filtered SDA line transitions to a ‘1’, when the SCL line is
high.
Figure 28-7. Stop Status and Interrupt Timing
Figure 28-8 illustrates the timing for bus error interrupts. Bus
Error status (and Interrupt) occurs one cycle after the inter-
nal Start or Stop Detect (two cycles after the filtered and
synced SDA input transition).
Figure 28-8. Bus Error Interrupt Timing
3 Cycles
Latency
CLOCK
Transmit: Ninth positive edge SCL
Receive: Eighth positive edge SCL
SCL
SCL_IN
(Synchronized)
IRQ
Max
CLOCK
SCL
SDA_IN
(Synchronized)
STOP IRQ
and STATUS
SDA
STOP DETECT
CLOCK
SCL
SDA_IN
(Synchronized)
BUS ERROR
and INTERRUPT
SDA
START DETECT
Misplaced Start
Misplaced Stop
CLOCK
SCL
SDA_IN
(Synchronized)
BUS ERROR
and INTERRUPT
SDA
STOP DETECT