Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 195
Digital Blocks
17.2.5 DxBxxIN Registers
The Digital Basic/Communications Type B Block Input Reg-
isters (DxBxxIN) are used to select the data and clock
inputs.
These registers are common to all functional types, except
the SPIS. The SPIS is unique in that it has three function
inputs and one function output defined. Refer to the
DxBxxOU registers.
The input registers are eight bits and consist of two 4-bit
fields to control each of the 16-to-1 clock and data input
muxes. The meaning of these fields depends on the exter-
nal clock and data connections, which is context specific.
See
Table 17-16 .
Bits 7 to 4:Data Input[3:0]. These bits control the data
input.
Bits 3 to 0: Clock Input[3:0]. These bits control the clock
input.
* The dead band reference input does not use the auxiliary input mux. It is
hardwired to be the primary output of the previous block.
** For CRC computation, the input data is a serial data stream synchronized
to the clock. For PRS mode, this input should be forced to logic 0.
For additional information, refer to the DxBxxIN register on
page 129 .
Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,xxh DxBxxIN Data Input[3:0] Clock Input[3:0] RW : 00
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
refer to the
“Digital Register Summary” on page 162
.
Table 17-16. Digital Block Input Definitions
Function
Inputs
DATA CLK Auxiliary
Timer Capture CLK N/A
Counter Enable CLK N/A
Dead Band Kill CLK Reference *
CRCPRS Serial Data ** CLK N/A
SPIM MISO CLK N/A
SPIS MOSI SCLK SS_
Transmitter N/A 8X Baud CLK N/A
Receiver RXD 8X Baud CLK N/A