162
Document # 001-20559 Rev. *D
Section D: Digital System
Digital Register Summary
The table below lists all the PSoC registers for the digital system in address order (Add. column) within their system resource
configuration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a
value of ‘0’. The naming conventions for the digital row registers and the digital block registers are detailed in their respective
table title rows.
Note that the CY8C24533, CY8C23533, CY8C23433CY8C24633 are 1 row devices.
Summary Table of the Digital Registers
Add.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
GLOBAL DIGITAL INTERCONNECT (GDI) REGISTERS
1,D0h
GIONOUT7
GIONOUT6
GIONOUT5
GIONOUT4
GIONOUT3
GIONOUT2
GIONOUT1
GIONOUT0
RW : 00
1,D1h
GIENOUT7
GIENOUT6
GIENOUT5
GIENOUT4
GIENOUT3
GIENOUT2
GIENOUT1
GIENOUT0
RW : 00
1,D2h
GOOUTIN7
GOOUTIN6
GOOUTIN5
GOOUTIN4
GOOUTIN3
GOOUTIN2
GOOUTIN1
GOOUTIN0
RW : 00
1,D3h
GOEUTIN7
GOEUTIN6
GOEUTIN5
GOEUTIN4
GOEUTIN3
GOEUTIN2
GOEUTIN1
GOEUTIN0
RW : 00
DIGITAL ROW REGISTERS
(page
x,B0h
RI0[1:0]
RW : 00
x,B1h
RI0SYN
RW : 00
x,B2h
BCSEL[1:0]
IS3
IS2
IS1
IS0
RW : 00
x,B3h
LUT1[3:0]
LUT0[3:0]
RW : 00
x,B4h
LUT3[3:0]
LUT2[3:0]
RW : 00
x,B5h
GOO5EN
GOO1EN
GOE5EN
GOE1EN
GOO4EN
GOO0EN
GOE4EN
GOE0EN
RW : 00
x,B6h
GOO7EN
GOO3EN
GOE7EN
GOE3EN
GOO6EN
GOO2EN
GOE6EN
GOE2EN
RW : 00
DIGITAL BLOCK REGISTERS
(page
Digital Block Data and Control Registers
(page
)
0,20h
Data[7:0]
# : 00
0,21h
Data[7:0]
W : 00
0,22h
Data[7:0]
# : 00
0,23h
Function control/status bits for selected function[6:0]
Enable
# : 00
1,20h
Data Invert
BCEN
End Single
Mode[1:0]
Function[2:0]
RW : 00
1,21h
Data Input[3:0]
Clock Input[3:0]
RW : 00
1,22h
AUXCLK
AUXEN
AUX IO Select[1:0]
OUTEN
Output Select[1:0]
RW : 00
0,24h
Data[7:0]
# : 00
0,25h
Data[7:0]
W : 00
0,26h
Data[7:0]
# : 00
0,27h
Function control/status bits for selected function[6:0]
Enable
# : 00
1,24h
Data Invert
BCEN
End Single
Mode[1:0]
Function[2:0]
RW : 00
1,25h
Data Input[3:0]
Clock Input[3:0]
RW : 00
1,26h
AUXCLK
AUXEN
AUX IO Select[1:0]
OUTEN
Output Select[1:0]
RW : 00
0,28h
Data[7:0]
# : 00
0,29h
Data[7:0]
W : 00
0,2Ah
Data[7:0]
# : 00
0,2Bh
Function control/status bits for selected function[6:0]
Enable
# : 00
1,28h
Data Invert
BCEN
End Single
Mode[1:0]
Function[2:0]
RW : 00
1,29h
Data Input[3:0]
Clock Input[3:0]
RW : 00
1,2Ah
AUXCLK
AUXEN
AUX IO Select[1:0]
OUTEN
Output Select[1:0]
RW : 00
Summary of Contents for PSoC CY8C23533
Page 4: ...Contents Overview 4 Document 001 20559 Rev D Section G Glossary 385 Index 401 ...
Page 16: ...Contents Overview 16 Document 001 20559 Rev D ...
Page 24: ...24 Document 001 20559 Rev D Section A Overview ...
Page 30: ...30 Document 001 20559 Rev D Pin Information ...
Page 54: ...54 Document 001 20559 Rev D Supervisory ROM SROM ...
Page 60: ...60 Document 001 20559 Rev D RAM Paging ...
Page 68: ...68 Document 001 20559 Rev D Interrupt Controller ...
Page 76: ...12 Document 001 20559 Rev D General Purpose IO GPIO ...
Page 82: ...18 Document 001 20559 Rev D Internal Main Oscillator IMO ...
Page 84: ...20 Document 001 20559 Rev D Internal Low Speed Oscillator ILO ...
Page 90: ...26 Document 001 20559 Rev D External Crystal Oscillator ECO ...
Page 94: ...30 Document 001 20559 Rev D Phase Locked Loop PLL ...
Page 106: ...42 Document 001 20559 Rev D Sleep and Watchdog ...
Page 228: ...164 Document 001 20559 Rev D Section D Digital System ...
Page 234: ...170 Document 001 20559 Rev D Array Digital Interconnect ADI ...
Page 278: ...214 Document 001 20559 Rev D Digital Blocks ...
Page 296: ...232 Document 001 20559 Rev D Analog Interface ...
Page 304: ...240 Document 001 20559 Rev D Analog Array ...
Page 308: ...244 Document 001 20559 Rev D Analog Input Configuration ...
Page 312: ...248 Document 001 20559 Rev D Analog Reference ...
Page 338: ...274 Document 001 20559 Rev D Section F System Resources ...
Page 354: ...290 Document 001 20559 Rev D Multiply Accumulate MAC ...
Page 374: ...310 Document 001 20559 Rev D I2C ...
Page 400: ...336 Document 001 20559 Rev D Section G Glossary ...