Document # 001-20559 Rev. *D
173
Row Digital Interconnect (RDI)
16.2
Register Definitions
The following registers are associated with the Row Digital Interconnect (RDI) and are listed in address order. Each register
description has an associated register table showing the bit structure for that register. For a complete table of RDI registers,
refer to the
“Summary Table of the Digital Registers” on page 162
.
Only certain bits are accessible to be read or written. The bits that are grayed out throughout this manual are reserved bits
and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’.
The only configurable inputs to a digital PSoC block row are the Global Input Even and Global Input Odd 8-bit buses. The only
configurable outputs from the digital PSoC block row are the Global Output Even and Global Output Odd 8-bit buses.
illustrates the relationships between global signals and row signals.
16.2.1
RDIxRI Register
The Row Digital Interconnect Row Input Register (RDIxRI)
is used to control the input mux that determines which global
inputs drive the row inputs.
The RDIxRI Register and the
are the
only two registers that affect digital PSoC row input signals.
All other registers are related to output signal configuration.
The RDIxRI register has select bits that control four muxes,
where “x” denotes a place holder for the row index.
lists the meaning for each mux’s four possible
settings.
Bits 1 and 0: RI0[1:0].
These bits control the input mux for
row 0.
For additional information, refer to the
.
16.2.2
RDIxSYN Register
The Row Digital Interconnect Synchronization Register
(RDIxSYN) is used to control the input synchronization.
The
and the RDIxSYN Register are the
only two registers that affect digital PSoC row input signals.
All other registers are related to output signal configuration.
By default, each row input is double synchronized to the
SYSCLK (system clock), which runs at 24 MHz unless exter-
nal clocking mode is enabled. However, a user may choose
to disable this synchronization by setting the appropriate
RIxSYN bit in the RDIxSYN register.
lists the bit
meanings for each implemented bit of the RDIxSYN register.
Bit 0: RI0SYN.
This bit controls the input synchronization
for row 0.
For additional information, refer to the
.
Add.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
x,B0h
RI0[1:0]
RW : 00
LEGEND
x
An “x” before the comma in the address field indicates that the register exists in both register banks.
Table 16-1. RDIxRI Register
RI0[1:0]
0h: GIE[0]
1h: GIE[4]
2h: GIO[0]
3h: GIO[4]
Add.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
x,B1h
RI0SYN
RW : 00
LEGEND
x
An “x” before the comma in the address field indicates that the register exists in both register banks.
Table 16-2. RDIxSYN Register
RI0SYN
0: Row input 0 is synchronized to SYSCLK
1: Row input 0 is passed without synchronization
Summary of Contents for PSoC CY8C23533
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Page 68: ...68 Document 001 20559 Rev D Interrupt Controller ...
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Page 82: ...18 Document 001 20559 Rev D Internal Main Oscillator IMO ...
Page 84: ...20 Document 001 20559 Rev D Internal Low Speed Oscillator ILO ...
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Page 228: ...164 Document 001 20559 Rev D Section D Digital System ...
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Page 278: ...214 Document 001 20559 Rev D Digital Blocks ...
Page 296: ...232 Document 001 20559 Rev D Analog Interface ...
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