Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 5
6. General Purpose IO (GPIO)
This chapter discusses the General Purpose IO (GPIO) and its associated registers, which is the circuit responsible for inter-
facing to the IO pins of a PSoC device. The GPIO blocks provide the interface between the M8C core and the outside world.
They offer a large number of configurations to support several types of
input/output (IO) operations for both digital and ana-
log systems. For a complete table of the GPIO registers, refer to the “Summary Table of the Core Registers” on page 32 . For
a quick reference of all PSoC registers in address order, refer to the Register Details chapter on page 47 .
6.1 Architectural Description
The GPIO contains input buffers, output drivers, register bit
storage, and configuration logic for connecting the PSoC
device to the outside world.
IO ports are arranged with (up to) 8 bits per port. Each full
port contains eight identical GPIO blocks, with connections
to identify a unique address and register bit number for each
block. Each GPIO block can be used for the following types
of IO:
■ Digital IO (digital input and output controlled by software)
■ Global IO (digital PSoC block input and output)
■ Analog IO (analog PSoC block input and output)
Each IO pin also has several drive modes, as well as inter-
rupt capabilities. While all GPIO pins are identical and pro-
vide digital IO, some pins may not connect internally to
analog functions.
The main block diagram for the GPIO block is shown in
Figure 6-1 . Note that some pins do not have all of the func-
tionality shown, depending on internal connections.
6.1.1 Digital IO
One of the basic operations of the GPIO ports is to allow the
M8C to send information out of the PSoC device and get
information into the M8C from outside the PSoC device.
This is accomplished by way of the port data register
(PRTxDR). Writes from the M8C to the PRTxDR register
store the data state, one bit per GPIO. In the standard non-
bypass mode, the pin drivers drive the pin in response to
this data bit, with a drive strength determined by the Drive
mode setting (see
Figure 6-1 ). The actual voltage on the pin
depends on the Drive mode and the external load .
The M8C can read the value of a port by reading the
PRTxDR register address. When the M8C reads the
PRTxDR register address, the current value of the pin volt-
age is translated into a logic value and returned to the M8C.
Note that the pin voltage can represent a different logic
value than the last value written to the PRTxDR register.
This is an important distinction to remember in situations
such as the use of a read modify write to a PRTxDR register.
Examples of read modify write instructions include
AND ,
OR , and XOR .
The following is an example of how a read modify write, to a
PRTxDR register, can have an unexpected and even inde-
terminate result in certain systems. Consider a scenario
where all bits of Port 1 on the PSoC device are in the Strong
1 Resistive 0 Drive mode; so that in some cases, the system
the PSoC is in may pull up one of the bits.
mov reg[PRT1DR], 0x00
or reg[PRT1DR], 0x80
In the first line of code above, writing a 0x00 to the port does
not affect any bits that happen to be driven by the system
the PSoC is in. However, in the second line of code, it does
not guarantee that only bit 7 is the one set to a strong 1.
Because the OR instruction first reads the port, any bits that
are in the pull up state are read as a ‘1’. These ones are
then written back to the port. When this happens, the pin
goes into a strong 1 state; therefore, if the pull up condition
ends in the system, the PSoC keeps the pin value at a logic
1.