Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 177
17. Digital Blocks
This chapter covers the configuration and use of the digital PSoC blocks and their associated registers. For a complete table
of the Digital PSoC Block registers, refer to the
“Summary Table of the Digital Registers” on page 162 . For a quick reference
of all PSoC registers in address order, refer to the Register Details chapter on page 47 .
17.1 Architectural Description
At the top level, the main components of the digital block are the data path, input multiplexers (muxes), output de-muxes, con-
figuration registers, and chaining signals (see
Figure 17-1 ).
Figure 17-1. Digital Blocks Top-Level Block Diagram
All digital PSoC blocks may be configured to perform any
one of five basic functions: timer, counter,
pulse width
modulator (PWM) , pseudo random sequence (PRS), or
cyclic redundancy check (CRC) . These functions may be
used by configuring an individual PSoC block or chaining
several PSoC blocks together to form functions that are
greater than 8 bits. Digital communications PSoC blocks
have two additional functions: master or slave SPI and a full
duplex
UART .
Each digital PSoC block’s function is independent of all
other PSoC blocks. Up to seven registers are used to deter-
mine the function and state of a digital PSoC block. These
registers are discussed in the
Register Definitions section.
Digital PSoC block function registers end with FN. The indi-
vidual bit settings for a block’s function register are listed in
Table 17-14 on page 194 . The input registers end with IN
and its bit meanings are listed in Table 17-16 on page 195 .
16-1
MUX
16-1
MUX
4-1
MUX
CLK
Re-
Sync
Clock
Select
Data
Select
Aux
Data
Select
Digital PSoC Block
1-4
DMUX
Primary
Function Output,
clock chaining to
next block.
RO[3:0]
RO[3:0]
1-4
DMUX
Block Interrupt
Broadcast Output
Configuration Registers
FUNCTION[7:0] INPUT[7:0] OUTPUT[7:0]
AUX_DATA
Data Path
F1
F2
INT
BC
CLK
DATA