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318

Document # 001-20559 Rev. *D

System Resets

30.4.3

Reset Details

Timing and functionality details are summarized in

shows some of the relevant signals for IPOR and

PPOR, and XRES, while

shows signaling for WDR .

30.5

Power Consumption

The ILO block drives the CLK32K clock used to time most
events during the reset sequence. This clock is powered
down by IPOR, but not by any other reset. The sleep timer
provides interval timing.

While POR or XRES asserts, the IMO is powered off to
reduce start up power consumption.

During and after POR or XRES, the bandgap circuit is pow-
ered up.

The IMO is always on for at least one CLK32K cycle, before
CPU reset is de-asserted.

Table 30-1. Details of Functionality for Various Resets

Item

IPOR (Part of POR)

PPOR (Part of POR)

XRES

WDR

Reset Length

While POR=1

While PPOR=1, plus

30-60



s (1-2 clocks)

While XRES=1

30



s (1 clock)

Low Power (IMO Off) During Reset

Yes

Yes

Yes

No

Low Power Wait Following Reset

No

No

No

No

CLK32K Cycles from End of Reset to

CPU Reset De-asserts

a

a. CPU reset is released after synchronization with the CPU Clock.

512

1

8

1

Register Reset

(See next line for CPU_SCR0,
CPU_SCR1)

All

All, except PPOR does not

reset Bandgap Trim

register

All

All

Reset Status Bits in CPU_SCR0,
CPU_SCR1

Set PORS,

Clear WDRS,

Clear IRAMDIS

Set PORS,

Clear WDRS,

Clear IRAMDIS

Set PORS,

Clear WDRS,

Clear IRAMDIS

Clear PORS,

Set WDRS,

IRAMDIS unchanged

Bandgap Power

On

On

On

On

Boot Time

b

b. Measured from CPU reset release to execution of the code at Flash address 0x0000.

2.2 ms

2.2 ms

2.2 ms

2.2 ms

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Summary of Contents for PSoC CY8C23533

Page 1: ... PSoC CY8C24533 CY8C23533 CY8C23433 Technical Reference Manual TRM Document 001 20559 Rev D January 19 2017 Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 Phone USA 800 858 1810 Phone Intnl 408 943 2600 http www cypress com ...

Page 2: ...NESS FOR A PARTICULAR PUR POSE To the extent permitted by applicable law Cypress reserves the right to make changes to this document without fur ther notice Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document Any information provided in this document including any sample design information or programming code is provided ...

Page 3: ...C Register Reference 107 13 Register Details 111 Section D Digital System 225 14 Global Digital Interconnect GDI 229 15 Array Digital Interconnect ADI 233 16 Row Digital Interconnect RDI 235 17 Digital Blocks 241 Section E Analog System 279 18 Analog Interface 283 19 Analog Array 297 20 Analog Input Configuration 305 21 Analog Reference 309 22 Continuous Time PSoC Block 313 23 Switched Capacitor P...

Page 4: ...Contents Overview 4 Document 001 20559 Rev D Section G Glossary 385 Index 401 ...

Page 5: ... Units of Measure 22 Acronyms 23 1 Pin Information 25 1 1 Pinouts 25 1 1 1 28 Pin Part Pinout 26 1 1 2 32 Pin Part Pinout 28 1 1 3 56 Pin Part Pinout 29 Section B PSoC Core 31 Top Level Core Architecture 31 Interpreting Core Documentation 31 Core Register Summary 32 2 CPU Core M8C 35 2 1 Overview 35 2 2 Internal Registers 35 2 3 Address Spaces 35 2 4 Instruction Set Summary 36 2 5 Instruction Form...

Page 6: ...9 3 1 2 7 EraseAll Function 49 3 1 2 8 Checksum Function 50 3 1 2 9 Calibrate0 Function 50 3 1 2 10 Calibrate1 Function 50 3 2 Register Definitions 51 3 2 1 CPU_SCR1 Register 51 3 2 2 FLS_PR1 Register 52 3 3 Clocking 53 3 3 1 DELAY Parameter 53 3 3 2 CLOCK Parameter 53 4 RAM Paging 55 4 1 Architectural Description 55 4 1 1 Basic Paging 55 4 1 2 Stack Operations 56 4 1 3 Interrupts 56 4 1 4 MVI Ins...

Page 7: ...O 79 8 1 Architectural Description 79 8 2 Application Description 79 8 2 1 Trimming the IMO 79 8 3 Register Definitions 80 8 3 1 CPU_SCR1 Register 80 8 3 2 OSC_CR2 Register 81 8 3 3 IMO_TR Register 81 9 Internal Low Speed Oscillator ILO 83 9 1 Architectural Description 83 9 2 Register Definitions 83 9 2 1 ILO_TR Register 83 10 External Crystal Oscillator ECO 85 10 1 Architectural Description 85 10...

Page 8: ...r Space 108 Register Map Bank 1 Table Configuration Space 109 13 Register Details 111 13 1 Maneuvering Around the Registers 111 Register Conventions 112 13 1 1 Register Naming Conventions 112 13 2 Bank 0 Registers 113 13 2 1 PRTxDR 113 13 2 2 PRTxIE 114 13 2 3 PRTxGS 115 13 2 4 PRTxDM2 116 13 2 5 DxBxxDR0 117 13 2 6 DxBxxDR1 118 13 2 7 DxBxxDR2 119 13 2 8 DxBxxCR0 Timer Control 120 13 2 9 DxBxxCR0...

Page 9: ...13 2 46 I2C_DR 161 13 2 47 I2C_MSCR 162 13 2 48 INT_CLR0 163 13 2 49 INT_CLR1 165 13 2 50 INT_CLR3 166 13 2 51 INT_MSK3 167 13 2 52 INT_MSK0 168 13 2 53 INT_MSK1 169 13 2 54 INT_VC 170 13 2 55 RES_WDT 171 13 2 56 DEC_DH 172 13 2 57 DEC_DL 173 13 2 58 DEC_CR0 174 13 2 59 DEC_CR1 175 13 2 60 MULx_X 176 13 2 61 MULx_Y 177 13 2 62 MULx_DH 178 13 2 63 MULx_DL 179 13 2 64 MACx_X ACCx_DR1 180 13 2 65 MAC...

Page 10: ...220 13 3 32 ILO_TR 221 13 3 33 BDG_TR 222 13 3 34 ECO_TR 223 13 3 35 FLS_PR1 224 Section D Digital System 225 Top Level Digital Architecture 225 Interpreting the Digital Documentation 225 Digital Register Summary 226 14 Global Digital Interconnect GDI 229 14 1 Architectural Description 229 14 1 1 28 Pin Global Interconnect 230 14 2 Register Definitions 231 14 2 1 GDI_x_IN Registers 231 14 2 2 GDI_...

Page 11: ...7 1 11 SPI Master Function 247 17 1 11 1 Usability Exceptions 248 17 1 11 2 Block Interrupt 248 17 1 12 SPI Slave Function 248 17 1 12 1 Usability Exceptions 248 17 1 12 2 Block Interrupt 248 17 1 13 Asynchronous Transmitter and Receiver Functions 249 17 1 13 1 Asynchronous Transmitter Function 249 17 1 13 2 Usability Exceptions 249 17 1 13 3 Block Interrupt 249 17 1 13 4 Asynchronous Receiver Fun...

Page 12: ... Interface 284 18 1 3 Analog Column Clock Generation 285 18 1 3 1 Column Clock Synchronization 285 18 1 4 Decimator and Incremental ADC Interface 285 18 1 4 1 Decimator 285 18 1 4 2 Incremental ADC 285 18 1 5 Analog Modulator Interface Mod Bits 286 18 1 6 Analog Synchronization Interface Stalling 286 18 2 PSoC Device Distinctions 286 18 3 Application Description 286 18 3 1 SAR Hardware Acceleratio...

Page 13: ...22 1 Architectural Description 313 22 2 Register Definitions 315 22 2 1 ACBxxCR3 Register 315 22 2 2 ACBxxCR0 Register 317 22 2 3 ACBxxCR1 Register 317 22 2 4 ACBxxCR2 Register 318 23 Switched Capacitor PSoC Block 319 23 1 Architectural Description 319 23 2 Application Description 321 23 3 Register Definitions 322 23 3 1 ASCxxCR0 Register 323 23 3 2 ASCxxCR1 Register 324 23 3 3 ASCxxCR2 Register 3...

Page 14: ...SC_CR1 Register 347 25 3 8 OSC_CR2 Register 348 26 Multiply Accumulate MAC 349 26 1 Architectural Description 349 26 2 Application Description 350 26 2 1 Multiplication with No Accumulation 350 26 2 2 Accumulation After Multiplication 350 26 3 Register Definitions 351 26 3 1 MULx_X Register 351 26 3 2 MULx_Y Register 351 26 3 3 MULx_DH Register 352 26 3 4 MULx_DL Register 352 26 3 5 MACx_X ACCx_DR...

Page 15: ...9 Master Clock Synchronization 373 29 Internal Voltage Reference 375 29 1 Architectural Description 375 29 2 Register Definitions 376 29 2 1 BDG_TR Register 376 30 System Resets 377 30 1 Architectural Description 377 30 2 Pin Behavior During Reset 377 30 2 1 GPIO Behavior on Power Up 377 30 3 Register Definitions 378 30 3 1 CPU_SCR1 Register 378 30 3 2 CPU_SCR0 Register 379 30 4 Timing Diagrams 38...

Page 16: ...Contents Overview 16 Document 001 20559 Rev D ...

Page 17: ...iagrams The sections are as follows Overview Presents the PSoC top level architecture PSoC device characteristics and distinctions how to get started with helpful information and document history and conventions The PSoC device pinouts are detailed in the Pin Information chapter on page 25 PSoC Core Describes the heart of the PSoC device in various chapters beginning with an architectural overview...

Page 18: ...cts GDI ADI and RDI respectively The digital system block is composed of 4 digital PSoC blocks Each block is an 8 bit resource that can be used alone or combined with other blocks to form 8 16 24 and 32 bit peripherals which are called user modules The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin The buses also allow for signal m...

Page 19: ...l Interconnect Global Analog Interconnect PSoC CORE CPU Core M8C SROM Flash 8K Multiply Accum MAC Internal Voltage Ref Digital Clocks POR and LVD System Resets Decimator SYSTEM RESOURCES ANALOG SYSTEM Analog Ref I2 C Port 2 Port 1 Port 0 Analog Drivers System Bus Analog Block Array Digital PSoC Block Array DBB0 1 DBB0 0 DCB02 DCB03 SAR8 ADC SC SC CT Analog Input Muxing 1 Digital Row 2 Analog Colum...

Page 20: ...System Resets Decimator Multiply Accumulate SAR8 ADC XRES Pin CY8C24423A T1 1 CY8C24533 T1 1 CY8C23533 T1 1 CY8C23433 T1 1 CY8C24633 T1 1 PSoC Device Distinctions Device Distinctions Devices Affected Described in Chapter Low Power Oscillator Capability The slow IMO SLIMO bit is available to enable SYSCLK operation at 6 MHz and 12 MHz instead of only 24 MHz The SLIMO bit is located in the CPU_SCR1 ...

Page 21: ...rsion enhancements for PSoC Designer free of charge You can order the upgrades from your distributor on CD ROM or download them directly from http www cypress com Development Kits Development Kits are available from the following distributors Digi Key Avnet Arrow and Future The Cypress Online Store contains development kits C compilers and all accessories for PSoC development Go to the Cypress Onl...

Page 22: ...by a 0x prefix the C coding convention Binary numbers have an appended lowercase b for example 01010100b or 01000011b Numbers not indicated by an h or b are decimal Units of Measure The following table lists the units of measure used in this manual Register Conventions Convention Example Description x in a register name ACBxxCR1 Multiple instances address ranges of the same register R R 00 Read re...

Page 23: ...nterrupt vector read LFSR linear feedback shift register LRb last received bit LRB last received byte LSb least significant bit LSB least significant byte LUT look up table MISO master in slave out MOSI master out slave in MSb most significant bit MSB most significant byte PC program counter PCH program counter high PCL program counter low PD power down PMA PSoC memory arbiter POR power on reset P...

Page 24: ...24 Document 001 20559 Rev D Section A Overview ...

Page 25: ...ckaging information refer to the individual PSoC device s data sheet at http www cypress com psoc 1 1 Pinouts The PSoC CY8C24533 CY8C23533 CY8C23433CY8C24633 are available in 28 pin SSOP and 32 pin QFN and 56 pin SSOP OCDpackages Refer to the following information for details Every port pin labeled with a P except for Vss and Vdd and XRES in the following tables and illustrations is capable of Dig...

Page 26: ...Active high pin reset with internal pull down 20 IO I P2 0 Direct switched capacitor input 21 IO I P2 2 Direct switched capacitor input 22 IO P2 4 GPIO 23 IO P2 6 GPIO 24 IO I P0 0 Analog Col Mux IP and ADC IP 25 IO I P0 2 Analog Col Mux IP and ADC IP 26 IO I P0 4 Analog Col Mux IP and ADC IP 27 IO I P0 6 Analog Col Mux IP and ADC IP 28 Power Vdd Supply voltage LEGEND A Analog I Input and O Output...

Page 27: ...d Capacitor Input 21 IO I P2 2 Direct Switched Capacitor Input 22 IO P2 4 External Analog Ground AGnd 23 IO P2 6 Analog Voltage Reference VRef 24 IO I P0 0 Analog Column Mux IP and ADC IP 25 IO I P0 2 Analog Column Mux IP and ADC IP 26 IO I P0 4 Analog Column Mux IP and ADC IP 27 IO I P0 6 Analog Column Mux IP and ADC IP 28 Power Vdd Supply Voltage LEGEND A Analog I Input and O Output Even though ...

Page 28: ...21 IO P2 4 External Analog Ground AGnd 22 IO P2 6 External Voltage Reference VRef 23 IO I P0 0 Analog Column Mux Input and ADC Input 24 IO I P0 2 Analog Column Mux Input and ADC Input 25 NC No Connection 26 IO I P0 4 Analog Column Mux Input and ADC Input 27 IO I P0 6 Analog Column Mux Input and ADC Input 28 Power Vdd Supply Voltage 29 IO I P0 7 Analog Column Mux Input and ADC Input 30 IO IO P0 5 A...

Page 29: ... 31 P1 0 Crystal XTALout I2C Serial Data SDA 44 NC No internal connection 32 P1 2 45 NC No internal connection 33 P1 4 Optional External Clock Input EXTCLK 46 NC No internal connection 34 P1 6 47 NC No internal connection 35 NC No internal connection 48 P2 0 Direct switched capacitor block input AI 36 NC No internal connection 49 P2 2 Direct switched capacitor block input AI 37 P3 1 GPIO 50 P2 4 E...

Page 30: ...30 Document 001 20559 Rev D Pin Information ...

Page 31: ...e top level architecture of the PSoC s core Each component of the figure is discussed at length in this section PSoC Core Block Diagram Interpreting Core Documentation The core section covers the heart of the PSoC device which includes the M8C microcontroller SROM interrupt con troller GPIO analog output drivers and SRAM paging mul tiple clock sources such as IMO ILO ECO and PLL and sleep and watc...

Page 32: ... RL 02 SUPERVISORY ROM SROM REGISTERS page 51 x FEh CPU_SC R1 IRESS SLIMO ECO EXW ECO EX IRAMDIS 00 1 FAh FLS_PR1 Bank 1 0 RW 00 RAM PAGING SRAM REGISTERS page 58 x 6Ch TMP_DR 0 Data 7 0 RW 00 x 6Dh TMP_DR 1 Data 7 0 RW 00 x 6Eh TMP_DR 2 Data 7 0 RW 00 x 6Fh TMP_DR 3 Data 7 0 RW 00 x F7h CPU_F PgMode 1 0 XIO Carry Zero GIE RL 02 INTERRUPT CONTROLLER REGISTERS page 64 0 DAh INT_CLR 0 VC3 Sleep GPIO...

Page 33: ...ve Mode 0 7 0 RW 00 1 09h PRT2DM 1 Drive Mode 1 7 0 RW FF 1 0Ah PRT2IC0 Interrupt Control 0 7 0 RW 00 1 0Bh PRT2IC1 Interrupt Control 1 7 0 RW 00 0 0Ch PRT3DR Data 7 0 RW 00 0 0Dh PRT3IE Interrupt Enables 7 0 RW 00 0 0Eh PRT3GS Global Select 7 0 RW 00 0 0Fh PRT3DM 2 Drive Mode 2 7 0 RW FF 1 0Ch PRT3DM 0 Drive Mode 0 7 0 RW 00 1 0Dh PRT3DM 1 Drive Mode 1 7 0 RW FF 1 0Eh PRT3IC0 Interrupt Control 0 ...

Page 34: ... T WDSL_Clear 7 0 W 00 x FEh CPU_SC R1 IRESS SLIMO ECO EXW ECO EX IRAMDIS 00 x FFh CPU_SC R0 GIES WDRS PORS Sleep STOP XX 1 E0h OSC_CR 0 32k Select PLL Mode No Buzz Sleep 1 0 CPU Speed 2 0 RW 00 1 E9h ILO_TR Bias Trim 1 0 Freq Trim 3 0 W 00 1 EBh ECO_TR PSSDC 1 0 W 00 LEGEND L The and f expr or f expr and xor f expr instructions can be used to modify this register Access is bit specific Refer to t...

Page 35: ...points to the next stack byte in RAM If the last byte in the stack is at address FFh the stack pointer wraps to RAM address 00h It is the firmware developer s responsibility to ensure that the stack does not overlap with user defined variables in RAM With the exception of the F register the M8C internal regis ters are not accessible via an explicit register address The internal M8C registers are a...

Page 36: ...expr C Z 3E 10 2 MVI A expr Z 6B 7 2 RLC expr C Z 12 6 2 SUB A expr C Z 3F 10 2 MVI expr A 6C 8 2 RLC X expr C Z 13 7 2 SUB A X expr C Z 40 4 1 NOP 6D 4 1 RRC A C Z 14 7 2 SUB expr A C Z 41 9 3 AND reg expr expr Z 6E 7 2 RRC expr C Z 15 8 2 SUB X expr A C Z 42 10 3 AND reg X expr expr Z 6F 8 2 RRC X expr C Z 16 9 3 SUB expr expr C Z 43 9 3 OR reg expr expr Z 70 4 2 AND F expr C Z 17 10 3 SUB X exp...

Page 37: ...C Z 70 4 2 AND F expr C Z 5A 5 2 MOV expr X 12 6 2 SUB A expr C Z 41 9 3 AND reg expr expr Z 5B 4 1 MOV A X Z 13 7 2 SUB A X expr C Z 42 10 3 AND reg X expr expr Z 5C 4 1 MOV X A 14 7 2 SUB expr A C Z 64 4 1 ASL A C Z 5D 6 2 MOV A reg expr Z 15 8 2 SUB X expr A C Z 65 7 2 ASL expr C Z 5E 7 2 MOV A reg X expr Z 16 9 3 SUB expr expr C Z 66 8 2 ASL X expr C Z 5F 10 3 MOV expr expr 17 10 3 SUB X expr ...

Page 38: ... final category for one byte instructions are those that cause updates of the internal M8C registers This category holds the largest number of instructions ASL ASR CPL DEC INC MOV POP RET RETI RLC ROMX RRC SWAP These instructions can cause the A X and SP regis ters or SRAM to update 2 5 2 Two Byte Instructions The majority of M8C instructions are two bytes in length While these instructions can be...

Page 39: ... following is an example of this instruction MOV 7 5 2 6 Addressing Modes The M8C has ten addressing modes These modes are detailed and located on the following pages Source Immediate on page 39 Source Direct on page 40 Source Indexed on page 40 Destination Direct on page 41 Destination Indexed on page 41 Destination Direct Source Immediate on page 41 Destination Indexed Source Immediate on page 4...

Page 40: ...rmine the address of the source value in RAM or register address space The result of these instructions is placed in either the M8C A or X register as indicated by the instruction s opcode All instructions using the Source Indexed addressing mode are two bytes in length Source Indexed Examples Table 2 7 Source Direct Opcode Operand 1 Instruction Source Address Source Code Machine Code Comments ADD...

Page 41: ...All instructions using the Destination Direct Source Immediate addressing mode are three bytes in length Destination Direct Source Immediate Examples Table 2 9 Destination Direct Opcode Operand 1 Instruction Destination Address Source Code Machine Code Comments ADD 7 A 04 07 The value in the Accumulator is added to memory at address 7 The result is placed in memory at address 7 The Accumulator is ...

Page 42: ...in operand 2 of the instruction The instruction using the Destination Direct Source Direct addressing mode is three bytes in length Destination Direct Source Direct Example Table 2 12 Destination Indexed Source Immediate Opcode Operand 1 Operand 2 Instruction Destination Index Immediate Value Source Code Machine Code Comments ADD X 7 5 07 07 05 The value in memory at address X 7 is added to the im...

Page 43: ...value is stored The pointer s value is incremented after the value is written to the destination address For PSoC microcontrollers with more than 256 bytes of RAM the Data Page Write MVW_PP register is used to determine which RAM page to use with the destination address Therefore values can be stored in pages other than the current page without changing the Current Page Pointer CUR_PP The pointer ...

Page 44: ...2 Carry The Carry flag bit is set or cleared in response to the result of several instructions It can also be manipu lated by the flag logic opcodes for example OR F 4 See the PSoC Designer Assembly Guide User Manual for more details Bit 1 Zero The Zero flag bit is set or cleared in response to the result of several instructions It can also be manipu lated by the flag logic opcodes for example OR ...

Page 45: ...ote For PSoC devices with more than 256 bytes of SRAM that is more than 1 page of SRAM see the table titled PSoC Device SRAM Availability on page 55 the MVR_PP and the MVW_PP pointers are not disabled by clearing the CPU_F PgMode bits Therefore the POINTER parameter is interpreted as an address in the page indicated by the MVI page pointers when the supervisory operation is called This allows the ...

Page 46: ...PU_PC CPU_X CPU_F CPU_A to 00h writing 00h to most SRAM addresses in SRAM Page 0 and then begins to execute user code at address 0000h See Table 3 4 and the following paragraphs for more information on which SRAM addresses are modified If the checksum is not valid an internal reset is executed and the boot process starts over If this condition occurs the internal reset status bit IRESS is set in t...

Page 47: ...dress indicated by the value of the POINTER parameter When the ReadBlock completes successfully the accumulator KEY1 and KEY2 all have a value of 00h If the PSoC device has more than one bank of Flash the bank value in the FLS_PR1 register must be set prior to executing the SSC instruction Refer to Table 3 5 Note MVI expr A is used to store the Flash block contents in SRAM thus the MVW_PP register...

Page 48: ...has more than one bank of Flash the bank value in the FLS_PR1 register must be set prior to executing the SSC instruction Refer to Table 3 5 3 1 2 4 EraseBlock Function The EraseBlock function is used to erase a block of 64 con tiguous bytes in Flash The first thing the EraseBlock function does is check the protection bits and determine if the desired BLOCKID is writeable If write protection is tu...

Page 49: ... the unpro tected state This function may only be executed by an external programmer If EraseAll is executed from code the M8C halts without touching the Flash or protections Table 3 9 ProtectBlock Modes Mode Settings Description In PSoC Designer 00b SR ER EW IW Unprotected U Unprotected 01b SR ER EW IW Read protect F Factory upgrade 10b SR ER EW IW Disable external write R Field upgrade 11b SR ER...

Page 50: ...sh to their appropriate registers What is unique about Calibrate1 is that it calculates a checksum of the cali bration data and if that checksum is determined to be invalid Calibrate1 causes a hardware reset by generating an internal reset If this occurs it is indicated by setting the Internal Reset Status bit IRESS in the CPU_SCR1 register The Calibrate1 function uses SRAM to calculate a check su...

Page 51: ... as a status bit to indicate that the ECO EX bit has been previ ously written to It is read only Note that this bit cannot be used by the CY8C27x43 for silicon revision A and by the CY8C24533 CY8C23533 CY8C23433 CY8C24633 CY8C24x23 and CY8C22x13 PSoC devices Bit 2 ECO EX The ECO Exists bit serves as a flag to the hardware to indicate that an external crystal oscillator exists in the system Just af...

Page 52: ...mine the number of Flash banks in PSoC devices Bits 1 and 0 Bank 1 0 The Bank bits in this register indi cate which Flash bank the SROM Flash functions should operate on The default value for the Bank bit is zero Flash bank 0 holds up to the first 8K of user code as well as the cal table The optional Flash banks 1 2 and 3 hold addi tional user code For additional information refer to the FLS_PR1 r...

Page 53: ...lt must be determined These are device spe cific values that are stored in the Flash table 3 and are accessed by way of the TableRead SROM function see the TableRead Function on page 49 If the operating tempera ture is at or below 0 C the cold values should be used For operating temperatures at or above 0 C the hot values should be used See Table 3 11 for more information Equations for calculating...

Page 54: ...54 Document 001 20559 Rev D Supervisory ROM SROM ...

Page 55: ...y address bus allows the M8C to access up to 256 bytes of SRAM To increase the amount of SRAM the M8C accesses memory page bits The memory page bits are located in the CUR_PP register and allow for selection of one of eight SRAM pages In addition to setting the page bits Page mode must be enabled by setting the CPU_F 7 bit If Page mode is not enabled the page bits are ignored and all non stack mem...

Page 56: ...he ISR the previous SRAM address ing mode is restored when the CPU_F register value is restored by the RETI instruction Therefore all interrupt service routine code starts execution in SRAM Page 0 If it is necessary for the ISR to change to another SRAM page it can be accomplished by changing the values of the CPU_F 7 6 bits to enable the special SRAM addressing modes However any change made to th...

Page 57: ...to 00b In this mode index memory accesses are forced to SRAM Page 0 just as they would be in a PSoC device with only 256 bytes of SRAM This mode is also automatically enabled when an interrupt occurs in a PSoC device and is therefore consid ered the default ISR mode This is because before the ISR is entered the M8C pushes the current value of the CPU_F register on to the stack and then clears the ...

Page 58: ...d hardware do not use these registers and exist for the user to use as desired Bits 7 to 0 Data 7 0 Due to the paged SRAM architec ture of PSoC devices with more than 256 bytes of SRAM a value in SRAM may not always be accessible without first changing the current page The TMP_DRx registers are readable and writable registers that are provided to improve the performance of multiple SRAM page PSoC ...

Page 59: ...or more details Bit 1 Zero The Zero Flag bit is set or cleared in response to the result of several instructions It can also be manipu lated by the flag logic opcodes for example OR F 2 See the PSoC Designer Assembly Guide User Manual for more details Bit 0 GIE The state of the Global Interrupt Enable bit determines whether interrupts by way of the IRQ are rec ognized by the M8C This bit is set or...

Page 60: ...60 Document 001 20559 Rev D RAM Paging ...

Page 61: ...errupt is enabled through an update of an interrupt mask register or c an interrupt is pending and GIE is set from 0 to 1 in the CPU Flag register 2 The current executing instruction finishes 3 The internal interrupt routine executes taking 13 cycles During this time the following actions occur The PCH PCL and Flag register CPU_F are pushed onto the stack in that order The CPU_F register is then c...

Page 62: ...iority encoder see Figure 5 1 generates an interrupt vector for the highest priority interrupt that is pending 5 1 1 Posted versus Pending Interrupts An interrupt is posted when its interrupt conditions occur This results in the flip flop in Figure 5 1 clocking in a 1 The interrupt remains posted until the interrupt is taken or until it is cleared by writing to the appropriate INT_CLRx register A ...

Page 63: ...d or pending interrupts A software mechanism is provided to set individual interrupts Setting an interrupt by way of software is very useful during code development when one may not have the complete hardware system necessary to generate a real interrupt The following table lists the interrupts for all PSoC devices highlighting specifically the CY8C24533 CY8C23533 CY8C23433CY8C24633 and the priori...

Page 64: ...3 7 determines the way an individual bit value written to an INT_CLR0 register is interpreted When ENSWINT is cleared the default state writing 1 s to an INT_CLRx register has no effect However writing 0 s to an INT_CLRx register when ENSWINT is cleared causes the corresponding interrupt to clear If the ENSWINT bit is set any 0 s written to the INT_CLRx registers are ignored How ever 1 s written t...

Page 65: ...st even if its mask bit is zero All INT_MSKx bits are independent of all other INT_MSKx bits If an INT_MSKx bit is set the interrupt source associated with that mask bit may generate an interrupt that becomes a pending interrupt For example if INT_MSK0 5 is set and at least one GPIO pin is configured to generate an interrupt the interrupt controller allows a GPIO interrupt request to post and beco...

Page 66: ... Clear Register INT_VC returns the next pending interrupt and clears all pending interrupts when written Bits 7 to 0 Pending Interrupt 7 0 When the register is read the least significant byte LSB of the highest prior ity pending interrupt is returned For example if the GPIO and I2C interrupts are pending and the INT_VC register was read the value 1Ch is be read However if no interrupts are pending...

Page 67: ...the flag logic instructions for example OR F 1 GIE is also cleared automatically by the M8C upon entering the interrupt service routine ISR after the flag byte has been stored on the stack preventing nested interrupts Note that the bit can be set in an ISR if desired For GIE 1 the M8C samples the IRQ input for each instruc tion For GIE 0 the M8C ignores the IRQ For additional information refer to ...

Page 68: ...68 Document 001 20559 Rev D Interrupt Controller ...

Page 69: ...SoC device and get information into the M8C from outside the PSoC device This is accomplished by way of the port data register PRTxDR Writes from the M8C to the PRTxDR register store the data state one bit per GPIO In the standard non bypass mode the pin drivers drive the pin in response to this data bit with a drive strength determined by the Drive mode setting see Figure 6 1 The actual voltage o...

Page 70: ...sistive path 300 ohms directly through the GPIO block For analog modes the GPIO block is typically configured into a high impedance analog drive mode High Z The mode turns off the Schmitt trigger on the input path which may reduce power consumption and decrease inter nal switching noise when using a particular IO as an analog input Refer to the Electrical Specifications chapter in the device data ...

Page 71: ...ransitioned appropriately high or low to match the Interrupt mode configuration Once this happens the INTO line pulls low to assert the GPIO inter rupt This assumes the other system level enables are on such as setting the global GPIO interrupt enable and the Global Interrupt Enable Setting the pin interrupt enable may immediately assert INTO if the Interrupt mode conditions are already being met ...

Page 72: ...ding the PRTxDR register returns the actual pin state as seen by the input buffer This may not be the same as the expected output state if the load pulls the pin more strongly than the pin s configured output drive See Digital IO on page 5 for a detailed discussion of digital IO For additional information refer to the PRTxDR register on page 49 6 2 2 PRTxIE Registers The Port Interrupt Enable Regi...

Page 73: ...k is selected for global output the Global Output Bus drives to PIN bypass ing the data register value assuming I2C Enable 0 If the PRTxGS register is written to zero the global in out function is disabled for the pin and the pin reflects the value of PRT_DR For additional information refer to PRTxGS register on page 51 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0 xxh PRTx...

Page 74: ... Drive mode of high imped ance analog High Z This is achieved by forcing the reset state of all PRTxDM1 and PRTxDM2 registers to FFh The resistive drive modes place a resistance in series with the output for low outputs mode 000b or high outputs mode 011b Strong Drive mode 001b gives the fastest edges at high DC drive strength Mode 101b gives the same drive strength but with slower edges The open ...

Page 75: ...itches between low mode and high mode depending on the last value read from the port during reads of the data register PRTxDR If the last value read from the GPIO was 0 the GPIO subse quently is in Interrupt High mode If the last value read from the GPIO was 1 the GPIO then is in Interrupt Low mode Figure 6 3 GPIO Interrupt Mode 11b Figure 6 3 assumes that the GIE is set GPIO interrupt mask is set...

Page 76: ...12 Document 001 20559 Rev D General Purpose IO GPIO ...

Page 77: ... one analog block per column to drive a signal on its analog output bus ABUS to serve as the input to the ana log driver for that column The output from the analog output driver for each column can be enabled and disabled using the Analog Output Driver register ABF_CR0 If the analog output driver is enabled then it must have an analog block driving the ABUS for that column Otherwise the analog out...

Page 78: ...page 241 Bit 7 ACol1MUX A mux selects the output of column 0 input mux or column 1 input mux When set this bit sets the column 1 input to column 0 input mux output Bit 5 ABUF1EN Enables the analog output buffer for Ana log Column 1 Pin P0 5 A 0 disables the analog output buffer a 1 enables Bit 3 ABUF0EN Enables the analog output buffer for Ana log Column 0 Pin P0 3 1 Column AGND A 0 disables the a...

Page 79: ...quency doubler circuit which produces SYSCLKX2 can be disabled to save power The lower frequency SYS CLK settings are available by setting the slow IMO SLIMO bit in the CPU_SCR1 register With this bit set and the corre sponding factory trim value applied to the IMO_TR register SYSCLK can be lowered to 6 MHz This offers lower device power consumption for systems that can operate with the reduced sy...

Page 80: ...as been previ ously written to It is read only When this bit is a 1 this indi cates that the CPU_SCR1 register has been written to and is now locked When this bit is a 0 the register has not been written to since the last reset event Note that this bit cannot be used by the CY8C27x43 for silicon revision A and by the CY8C24533 CY8C23533 CY8C23433 CY8C24633 CY8C24x23 and CY8C22x13 PSoC devices Bit ...

Page 81: ...l device power on the order of 1 mA It is advised that any application that does not require this doubled clock should have it turned off For additional information refer to the OSC_CR2 register on page 153 8 3 3 IMO_TR Register The Internal Main Oscillator Trim Register IMO_TR is used to manually center the oscillator s output to a target fre quency The PSoC device specific value for 5V operation...

Page 82: ...18 Document 001 20559 Rev D Internal Main Oscillator IMO ...

Page 83: ... bit structure The bits in the table that are grayed out are reserved bits and are not detailed in the register description that follows Note that reserved bits should always be written with a value of 0 9 2 1 ILO_TR Register The Internal Low Speed Oscillator Trim Register ILO_TR sets the adjustment for the internal low speed oscillator The device specific value placed in the trim bits of this reg...

Page 84: ...20 Document 001 20559 Rev D Internal Low Speed Oscillator ILO ...

Page 85: ... the ECO is subsequently deacti vated the Internal Low Speed Oscillator ILO is again acti vated and the switch is made back to the ILO immediately The ECO Exists bit ECO EX bit 2 in the CPU_SCR1 regis ter is used to control whether the switch over is allowed or locked This is a write once bit It is written early in code exe cution after a Power On Reset POR or External Reset XRES event A 1 in this...

Page 86: ...e automatically done in boot asm Note 3 Transitions between oscillator domains may pro duce glitches on the 32 kHz clock bus Functions that require accuracy on the 32 kHz clock should be enabled after the transition in oscillator domains 10 1 1 ECO External Components The external component connections and selections of the External Crystal Oscillator are illustrated in Figure 10 2 Crystal 32 768 ...

Page 87: ...te that the ECO EX bit has been previ ously written to It is read only When this bit is a 1 this indi cates that the CPU_SCR1 register has been written to and is now locked When this bit is a 0 the register has not been written to since the last reset event Note that this bit cannot be used by the CY8C27x43 for silicon revision A and by the CY8C24533 CY8C23533 CY8C23433 CY8C24633 CY8C24x23 and CY8...

Page 88: ...he M8C s performance and power requirements to be tailored to the application The reset value for the CPU Speed bits is zero therefore the default CPU speed is one eighth of the clock source The Internal Main Oscillator IMO is the default clock source for the CPU speed circuit therefore the default CPU speed is 3 MHz The CPU frequency is changed with a write to the OSC_CR0 register There are eight...

Page 89: ...t boot time is based on factory testing This register does not adjust the frequency of the external crystal oscillator It is strongly recommended that the user not alter the register value Bits 7 and 6 PSSDC 1 0 These bits are used to set the sleep duty cycle These bits should not be altered For additional information refer to the ECO_TR register on page 159 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bi...

Page 90: ...26 Document 001 20559 Rev D External Crystal Oscillator ECO ...

Page 91: ...t put If longer lock time is tolerable the PLLGAIN bit can be held high all the time After the 32 768 kHz External Crystal Oscillator ECO has been selected and enabled the following procedure should be followed to enable the PLL and allow for proper fre quency lock Select a CPU frequency of 3 MHz or less Enable the PLL Wait between 10 and 50 ms depending on bit 7 of the OSC_CR2 register Set the CP...

Page 92: ...s 3 MHz The CPU frequency is changed with a write to the OSC_CR0 register There are eight frequencies generated from a power of two divide circuit which are selected by a 3 bit code At any given time the CPU 8 to 1 clock mux is selecting one of the available frequencies which is resyn chronized to the 24 MHz master clock at the output Regardless of the CPU Speed bit s setting if the actual CPU spe...

Page 93: ... functions All external and internal signals including the 32 kHz clock whether derived from the Internal Low Speed Oscillator ILO or the crystal oscillator are synchronized to this clock source If an external clock is enabled PLL mode should be off The external clock input is located on port P1 4 When using this input the pin Drive mode should be set to High Z not High Z analog Bit 1 RSVD Reserve...

Page 94: ...30 Document 001 20559 Rev D Phase Locked Loop PLL ...

Page 95: ...clock are examples of asynchronous interrupts that can also be used to wake the system up The Watchdog Timer WDT circuit is designed to assert a hardware reset to the device after a pre programmed inter val unless it is periodically serviced in firmware In the event that an unexpected execution path is taken through the code this functionality serves to reboot the system It also restarts the syste...

Page 96: ...evice enters Sleep mode the Sleep bit is cleared by the pending interrupt and Sleep mode is exited immediately Note 3 On wake up the instruction immediately after the sleep instruction is executed before the interrupt service routine if enabled The instruction after the sleep instruc tion is pre fetched before the system actually goes to sleep Therefore when an interrupt occurs to wake the system ...

Page 97: ...le For additional information refer to the INT_MSK0 register on page 104 12 3 2 RES_WDT Register The Reset Watchdog Timer Register RES_WDT is used to clear the watchdog timer a write of any value and clear both the watchdog timer and the sleep timer a write of 38h Bits 7 to 0 WDSL_Clear 7 0 The Watchdog Timer WDT write only register is designed to timeout at three roll over events of the sleep tim...

Page 98: ...not be used by the CY8C27x43 for silicon revision A and by the CY8C24533 CY8C23533 CY8C23433 CY8C24633 CY8C24x23 and CY8C22x13 PSoC devices Bit 2 ECO EX The ECO Exists bit serves as a flag to the hardware to indicate that an external crystal oscillator exists in the system Just after boot it may be written only once to a value of 1 crystal exists or 0 crystal does not exist If the bit is 0 a switc...

Page 99: ...en set To wake up the system this register bit is cleared asynchronously by any enabled interrupt There are two special features of this register bit that ensures proper sleep operation First the write to set the register bit is blocked if an interrupt is about to be taken on that instruction boundary immediately after the write Sec ond there is a hardware interlock to ensure that once set the Sle...

Page 100: ...s performance and power requirements to be tailored to the application The reset value for the CPU Speed bits is zero therefore the default CPU speed is one eighth of the clock source The Internal Main Oscillator IMO is the default clock source for the CPU speed circuit therefore the default CPU speed is 3 MHz The CPU frequency is changed with a write to the OSC_CR0 register There are eight freque...

Page 101: ...l information refer to the ILO_TR register on page 157 12 3 7 ECO_TR Register The External Crystal Oscillator Trim Register ECO_TR sets the adjustment for the 32 768 kHz external crystal oscil lator The value placed in this register is based on factory testing This register does not adjust the frequency of the external crystal oscillator It is strongly recommended that the user not alter the regis...

Page 102: ...signal In Figure 12 1 the CPU is halted and the system wide power down signal is asserted The system wide PD signal controls three major circuit blocks the Flash memory module the Internal Main Oscilla tor 24 48 MHz oscillator that is also called the IMO and the bandgap voltage reference These circuits transition into a zero power state The only operational circuits on the PSoC device are the ILO ...

Page 103: ... the 32 kHz clock 2 At the following positive edge of the 32 kHz clock the system wide PD signal is negated The Flash memory module IMO and bandgap any POR LVD circuits are all powered up to a normal operating state 3 At the next positive edge of the 32 kHz clock the values of the bandgap are settled and sampled 4 At the following negative edge of the 32 kHz clock after about 15 s nominal the valu...

Page 104: ... or XRES all code should be written as if it is enabled that is the WDT should be cleared period ically This is because in the initialization code after a WDR event the watchdog timer is enabled so all code must be aware of this The watchdog timer is three counts of the sleep timer inter rupt output The watchdog interval is three times the selected sleep timer interval The available selections for...

Page 105: ...ion consists of the items in the following tables In Table 12 5 the typical block currents shown do not repre sent maximums These currents do not include any analog block currents that may be on during Sleep mode While the CLK32K can be turned off in Sleep mode this mode is not useful since it makes it impossible to restart unless an Imprecise Power On Reset IPOR occurs The Sleep bit can not be cl...

Page 106: ...42 Document 001 20559 Rev D Sleep and Watchdog ...

Page 107: ...umn index Therefore ASD11CR3 is a register for an analog PSoC block in row 1 column 1 Register Mapping Tables The PSoC device has a total register address space of 512 bytes The register space is also referred to as IO space and is broken into two parts The XIO bit in the Flag register CPU_F determines which bank the user is currently in When the XIO bit is set the user is said to be in the extend...

Page 108: ...X_IN 60 RW 64 A0 INT_MSK0 E0 RW 104 DBB00DR1 21 W 54 61 A1 INT_MSK1 E1 RW 105 DBB00DR2 22 RW 55 62 A2 INT_VC E2 RC 106 DBB00CR0 23 56 ARF_CR 63 RW 65 A3 RES_WDT E3 W 107 DBB01DR0 24 53 CMP_CR0 64 66 A4 DEC_DH E4 RC 108 DBB01DR1 25 W 54 ASY_CR 65 67 A5 DEC_DL E5 RC 109 DBB01DR2 26 RW 55 CMP_CR1 66 RW 68 A6 DEC_CR0 E6 RW 110 DBB01CR0 27 56 SARADC_DL 67 RW 69 A7 DEC_CR1 E7 RW 111 DCB02DR0 28 53 A8 MU...

Page 109: ... DF RW 150 DBB00FN 20 RW 127 CLK_CR0 60 RW 133 A0 OSC_CR0 E0 RW 151 DBB00IN 21 RW 129 CLK_CR1 61 RW 134 A1 OSC_CR1 E1 RW 152 DBB00OU 22 RW 131 ABF_CR0 62 RW 135 A2 OSC_CR2 E2 RW 153 23 AMD_CR0 63 RW 136 A3 VLT_CR E3 RW 154 DBB01FN 24 RW 127 64 A4 VLT_CMP E4 R 155 DBB01IN 25 RW 129 65 A5 E5 DBB01OU 26 RW 131 AMD_CR1 66 RW 137 A6 E6 27 ALT_CR0 67 RW 138 A7 E7 DCB02FN 28 RW 127 68 SARADC_TRS A8 RW 13...

Page 110: ...A 7A BA FLS_PR1 FA RW 160 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU_SCR1 FE 121 3F 7F BF CPU_SCR0 FF 122 Name Addr 1 Hex Access Page Name Addr 1 Hex Access Page Name Addr 1 Hex Access Page Name Addr 1 Hex Access Page Gray fields are reserved Access is bit specific ...

Page 111: ...zation with reserved bits grayed out 3 Written description of register specifics or links to additional register information 4 Detailed register bit descriptions Note that some registers are directly related to the digital and analog functions therefore these registers might have more than one register table number 2 above This is due to the fact that the PSoC devices have different digital row an...

Page 112: ...R0 is a digital communication register for a digital PSoC block in row 3 column 2 For digital row registers the x in the digital register s name represents the digital row index For example the RDIxIS reg ister name encompasses four registers one for each digital row index and unique address RDI0IS RDI2IS and RDI3IS For analog column registers the naming convention for the switched capacitor and c...

Page 113: ...er has an address of x B4h and is in both Bank 0 and Bank 1 13 2 1 PRTxDR Port Data Register This register allows for write or read access of the current logical equivalent of the voltage on the pin For additional information refer to the Register Definitions on page 8 in the GPIO chapter 7 0 Data 7 0 Write value to port or read value from port Reads return the state of the pin not the value in th...

Page 114: ...tions on page 8 in the GPIO chapter 7 0 Interrupt Enables 7 0 A bit set in this register enables the corresponding port pin interrupt 0 Port pin interrupt disabled for the corresponding pin 1 Port pin interrupt enabled for the corresponding pin Individual Register Names and Addresses 0 01h PRT0IE 0 01h PRT1IE 0 05h PRT2IE 0 09h PRT3IE 0 0Dh 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name Interrupt Enabl...

Page 115: ...ing port pin to an internal global bus This connection is used to input or output digital signals to or from the digital blocks 0 Global function disabled The pin value is determined by the PRTxDR bit value and port configuration registers 1 Global function enabled Direction depends on mode bits for the pin registers PRTxDM0 PRTxDM1 and PRTxDM2 Individual Register Names and Addresses 0 02h PRT0GS ...

Page 116: ...d to as DM2 DM1 and DM0 or together as DM 2 0 All Drive mode bits are shown in the sub table below 210 refers to the combination in order of bits in a given bit position however this register only controls the most significant bit MSb of the Drive mode For additional information refer to the Register Definitions on page 8 in the GPIO chapter 7 0 Drive Mode 2 7 0 Bit 2 of the Drive mode for each pi...

Page 117: ...r B for basic or C for communication For rows of digital PSoC blocks and their registers the second x set represents Prefix mn Suffix where m row index n column index Therefore DBB21DR0 is a digital basic register for a digital PSoC block in row 2 column 1 For additional information refer to the Register Definitions on page 187 in the Digital Blocks chapter 7 0 Data 7 0 Data for selected function ...

Page 118: ... convention and digital row avail ability information For additional information refer to the Register Definitions on page 187 in the Digital Blocks chapter 7 0 Data 7 0 Data for selected function Block Function Register Function DCB Only Timer Period No Counter Period No Dead Band Period No CRCPRS Polynomial No SPIM TX Buffer Yes SPIS TX Buffer Yes TXUART TX Buffer Yes RXUART Not applicable Yes I...

Page 119: ...ormation For additional information refer to the Register Definitions on page 187 in the Digital Blocks chapter If the block is configured as SPIM SPIS or RXUART this register is read only 7 0 Data 7 0 Data for selected function Block Function Register Function DCB Only Timer Capture Compare No Counter Compare No Dead Band Buffer No CRCPRS Seed Residue No SPIM RX Buffer Yes SPIS RX Buffer Yes TXUA...

Page 120: ...For additional information refer to the Register Definitions on page 187 in the Digital Blocks chapter 2 TC Pulse Width Primary output 0 Terminal Count pulse width is one half a block clock Supports a period value of 00h 1 Terminal Count pulse width is one full block clock 1 Capture Int 0 Interrupt is selected with Mode bit 0 in the Function DxBxxFN register 1 Block interrupt is caused by a hardwa...

Page 121: ...ormation In the table above note that reserved bits are grayed table cells and are not described in the bit description section below Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 187 in the Digital Blocks chapter 0 Enable 0 Counter is not enabled 1 Counter is enabled Individual Register Names and Addresses 0 23h DBB00...

Page 122: ...ister Definitions on page 187 in the Digital Blocks chapter 2 Bit Bang Clock When Bit Bang mode is enabled the output of this register bit is substituted for the PWM reference This register may be toggled by user firmware to generate PHI1 and PH2 output clocks with the pro grammed dead time 1 Bit Bang Mode 0 Dead Band Generator uses the previous block primary output as the input reference 1 Dead B...

Page 123: ... below Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 187 in the Digital Blocks chapter 1 Pass Mode If selected the DATA input selection is driven directly to the primary output and the block interrupt output The CLK input selection is driven directly to the auxiliary output 0 Normal CRC PRS outputs 1 Outputs are overri...

Page 124: ...and all associated clocks are generated It is cleared on a read of this CR0 register Optional interrupt 4 TX Reg Empty Reset state and the state when the block is disabled is 1 0 Indicates that a byte is currently buffered in the TX register 1 Indicates that a byte is written to the TX register and cleared on write of the TX Buffer DR1 register This is the default interrupt This status is initiall...

Page 125: ... and all associated clocks are generated It is cleared on a read of this CR0 register Optional interrupt 4 TX Reg Empty Reset state and the state when the block is disabled is 1 0 Indicates that a byte is currently buffered in the TX register 1 Indicates that a byte is written to the TX register and cleared on write of the TX Buffer DR1 register This is the default interrupt This status is initial...

Page 126: ...ocess of shifting out 1 Indicates that a byte is shifted out and all associated framing bits are generated Optional interrupt Cleared on a read of this CR0 register 4 TX Reg Empty Reset state and the state when the block is disabled is 1 0 Indicates that a byte is currently buffered in the TX register 1 Indicates that a byte is written to the TX register and cleared on write of the TX Buffer regis...

Page 127: ...egister 5 Framing Error 0 Indicates no framing error has occurred 1 Valid when RX Reg Full is set indicating that a framing error has occurred a logic 0 was sampled at the STOP bit instead of the expected logic 1 It is cleared on a read of this CR0 register 4 RX Active 0 Indicates that no reception is in progress 1 Indicates that a reception is in progress It is set by the detection of a START bit...

Page 128: ...ed bits should always be written with a value of 0 For additional information refer to the Register Defini tions on page 243 in the Analog Input Configuration chapter 3 2 ACI1 1 0 Selects the Analog Column Mux 1 For 1 column these are even inputs 00b ACM1 P0 0 01b ACM1 P0 2 10b ACM1 P0 4 11b ACM1 P0 6 Note ACol1Mux ABF_CR0 Address 1 62h 0 AC1 ACM1 1 AC1 ACM0 1 0 ACI0 1 0 Selects the Analog Column ...

Page 129: ... for analog ground AGND the high reference RefHi and the low reference RefLo The following table applies to 2 column PSoC devices AGND RefHi RefLo 000b Vdd 2 Vdd 2 Bandgap Vdd 2 Bandgap 001b P2 4 P2 4 P2 6 P2 4 P2 6 010b Vdd 2 Vdd 2 Vdd 2 Vdd 2 Vdd 2 011b 2 x Bandgap 2 x Bandgap Bandgap 2 x Bandgap Bandgap 100b 2 x Bandgap 2 x Bandgap P2 6 2 x Bandgap P2 6 101b P2 4 P2 4 Bandgap P2 4 Bandgap 110b ...

Page 130: ...its are set then this bit is transpar ent to the comparator bus in the analog array 4 COMP 0 Comparator bus state for column 0 This bit is updated on the rising edge of PHI2 unless the comparator latch disable bits are set refer to the CLDISx bits in the CMP_CR1 register If the comparator latch disable bits are set then this bit is transpar ent to the comparator bus in the analog array 1 AINT 1 Co...

Page 131: ...in the analog array These bits must always be zero except for SAR processing 3 SARSIGN This bit adjusts the SAR comparator based on the type of block addressed In a DAC configuration with more than one analog block more than 6 bits this bit is set to 0 when processing the most sig nificant block It is set to 1 when processing the least significant block because the least significant block is an in...

Page 132: ...on to the detailed register bit descriptions below to determine which bits are reserved for some smaller PSoC devices Note that reserved bits are grayed table cells and are not described in the bit description sec tion below Reserved bits should always be written with a value of 0 For additional information refer to the Register Defini tions on page 227 in the Analog Interface chapter 5 CLDIS 1 Co...

Page 133: ...ns on page 266 in the SAR8 ADC Block chapter 7 0 Data 7 0 The read out data of this register is dependant on the right side scale bits setting which are defined in the SARADC_CR2 register The scale size setting affects the final read out results but not the ADC conversion results in this register Individual Register Names and Addresses 0 67h SARADC_DL 0 67h 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Nam...

Page 134: ...been read out 1 Start Busy 0 ADC has finished the operation If firmware writes a 1 to this bit it means that firmware trig gers the ADC to perform the sample and conversion from the next system clock cycle If this bit is already 1 in ADC conversion mode the new write of 1 forces the ADC to cancel the ongoing conversion and restart one new conversion from the next system clock cycle When the ADC is...

Page 135: ... inside VPWR P3 0 must be less than or equal to VPWR and ADC R2R reference generation block power supply must be less than or equal to that of the ADC analog block 1 ADC R2R reference generation block obtains power supply from P3 0 P3 0 must supply no less than 0 3 mA current 2 1 Align Source 1 0 00 Low and high channels are completely independent Both can trigger ADC Each is 8 bit accuracy 01 Onl...

Page 136: ...ices with 256 bytes of SRAM Refer to the table titled PSoC Device SRAM Availability on page 55 For additional information refer to the Register Definitions on page 58 in the RAM Paging chapter 7 0 Data 7 0 General purpose register space Individual Register Names and Addresses x 6Ch TMP_DR0 x 6Ch TMP_DR1 x 6Dh TMP_DR2 x 6Eh TMP_DR3 x 6Fh 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name Data 7 0 Bit Name D...

Page 137: ...description section below Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 251 in the Continuous Time Block chapter 3 LPCMPEN 0 Low power comparator is disabled 1 Low power comparator is enabled 2 CMOUT 0 No connection to column output 1 Connect Common mode to column output 1 INSAMP 0 Normal mode 1 Connect amplifiers acro...

Page 138: ...3 bit 0 EXGAIN The EXGAIN bit only affects the RTapMux values 0h and 1h RTap EXGAIN Rf Ri Loss Gain 0h 1 47 1 0 0208 48 000 1h 1 46 2 0 0417 24 000 0h 0 45 3 0 0625 16 000 1h 0 42 6 0 1250 8 000 2h 0 39 9 0 1875 5 333 3h 0 36 12 0 2500 4 000 4h 0 33 15 0 3125 3 200 5h 0 30 18 0 3750 2 667 6h 0 27 21 0 4375 2 286 7h 0 24 24 0 5000 2 000 8h 0 21 27 0 5625 1 778 9h 0 18 30 0 6250 1 600 Ah 0 15 33 0 6...

Page 139: ...n if bit 1 of the ACBxxCR3 register is set In that case the bottom of the resistor string is connected across columns Note that available mux inputs vary by individual PSoC block In the table below only columns ACB00 and ACB01 are used by the 2 column analog PSoC blocks ACB00 ACB01 00b ACB01 ACB00 01b AGND AGND 10b Vss Vss 11b Vss ASD11 ...

Page 140: ...output to analog column bus 6 CompBus Enable output to the comparator bus 0 Disable output to comparator bus 1 Enable output to comparator bus 5 3 NMux 2 0 Encoding for negative input select Note that available mux inputs vary by individual PSoC block In the table below only columns ACB00 and ACB01 are used by the 2 column analog PSoC blocks ACB00 ACB01 000b ACB01 ACB00 001b AGND AGND 010b RefLo R...

Page 141: ...vary by individual PSoC block The following table is used by the 2 column analog PSoC blocks ACB00 ACB01 000b RefLo Vss 001b Port Inputs Port Inputs 010b ACB01 ACB00 011b AGND AGND 100b Vss ASD11 101b ASD11 Vss 110b ABUS0 ABUS1 111b FB FB Feedback point from tap of the feedback resistor as defined by corresponding CR0 bits 7 4 and CR3 bit 0 ...

Page 142: ...ys transparent 1 Comparator Control latch is active 5 CompCap 0 Comparator Mode 1 Opamp Mode 4 TMUXEN Test Mux 0 Disabled 1 Enabled 3 2 TestMux 1 0 Select block bypass mode Note that available mux inputs vary by individual PSoC block and TMUXEN must be set In the table below columns ACB00 and ACB01 are used by the 2 column PSoC blocks ACB00 ACB01 00b Positive Input to ABUS0 ABUS1 01b AGND to ABUS0...

Page 143: ...arator within the switched capacitor blocks as well as the clock phase of the switches 0 Switch phasing is Internal PHI1 External PHI1 Comparator Capture Point Event is trig gered by Falling PHI2 and Comparator Output Point Event is triggered by Rising PHI1 1 Switch phasing is Internal PHI1 External PHI2 Comparator Capture Point Event is trig gered by Falling PHI1 and Comparator Output Point Event...

Page 144: ...258 in the Switched Capacitor Block chapter 7 5 AMux 2 0 Encoding for selecting A and C inputs for C Type blocks and A inputs for D Type blocks Note that available mux inputs vary by individual PSoC block In the table below only column ASD11 is used by the 2 column analog PSoC blocks The following table is used by the 2 column analog PSoC blocks ASD11 000b ACB01 001b P2 2 010b P2 3 011b ASC21 100b...

Page 145: ... bit 6 also effects this bit Sample Hold mode is allowed only if ClockPhase 0 0 Disable output to analog column bus 1 Enable output to analog column bus 6 CompBus Enable output to the comparator bus 0 Disable output to comparator bus 1 Enable output to comparator bus 5 AutoZero Bit for controlling the AutoZero switch 0 Shorting switch is not active Input cap branches shorted to opamp input 1 Short...

Page 146: ...g gated switches 0 Switch is disabled 1 If the FSW1 bit is set to 1 the state of the switch is determined by the AutoZero bit If the AutoZero bit is 0 the switch is enabled at all times If the AutoZero bit is 1 the switch is enabled only when the Internal PHI2 is high 4 FSW0 Bits for controlling gated switches 0 Switch is disabled 1 Switch is enabled when PHI1 is high 3 BSW Enable switching in bra...

Page 147: ...arator within the switched capacitor blocks as well as the clock phase of the switches 0 Switch phasing is Internal PHI1 External PHI1 Comparator Capture Point Event is trig gered by Falling PHI2 and Comparator Output Point Event is triggered by Rising PHI1 1 Switch phasing is Internal PHI1 External PHI2 Comparator Capture Point Event is trig gered by Falling PHI1 and Comparator Output Point Event...

Page 148: ...ormation refer to the Register Definitions on page 258 in the Switched Capacitor Block chapter 7 5 ACMux 2 0 Encoding to select A and C inputs Note that available mux inputs vary by individual PSoC block For 2 Column Analog PSoC Blocks ASC21 A Inputs C Inputs 000b ASD11 ASD11 001b P2 1 ASD11 010b RefHi ASD11 011b Vtemp ASD11 100b P2 3 ASD11 101b P2 1 ASD11 110b ABUS1 ASD11 111b P2 2 ASD11 4 0 BCap...

Page 149: ... page 83 bit 6 also affects this bit Sample Hold mode is allowed only if ClockPhase 0 0 Disable output to analog column bus 1 Enable output to analog column bus 6 CompBus Enable output to the comparator bus 0 Disable output to comparator bus 1 Enable output to comparator bus 5 AutoZero Bit for controlling gated switches 0 Shorting switch is not active Input cap branches shorted to opamp input 1 Sh...

Page 150: ... high the input is set to RefHi When set low the input is set to RefLo 5 FSW1 Bit for controlling the FSW1 switch 0 Switch is disabled 1 If the FSW1 bit is set to 1 the state of the switch is determined by the AutoZero bit If the AutoZero bit is 0 the switch is enabled at all times If the AutoZero bit is 1 the switch is enabled only when the Internal PHI2 is high 4 FSW0 Bit for controlling the FSW...

Page 151: ...s The x in the digital register s name represents the digital row index For additional information refer to the Register Defini tions on page 173 in the Row Digital Interconnect chapter 1 0 RI0 1 0 Select source for row input 0 00b GIE 0 01b GIE 4 10b GIO 0 11b GIO 4 Individual Register Names and Addresses x B0h RDI0RI x B0h 7 6 5 4 3 2 1 0 Access POR RW 0 Bit Name RI0 1 0 Bit Name Description ...

Page 152: ... table cells and are not described in the bit description section below Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 173 in the Row Digital Interconnect chapter 0 RI0SYN 0 Row input 0 is synchronized to the SYSCLK system clock 1 Row input 0 is passed without synchronization Individual Register Names and Addresses x B1...

Page 153: ...mber the tri state buffer that drives the row broadcast net from the input select mux is disabled so that one of the row s blocks may drive the local row broadcast net 00b Row 0 drives row broadcast net 01b Row 1 drives row broadcast net Reserved for 1 row PSoC devices 10b Row 2 drives row broadcast net Reserved for 1 and 2 row PSoC devices 11b Row 3 drives row broadcast net Reserved for 1 2 and 3...

Page 154: ...chapter 7 4 LUT1 3 0 Select logic function for LUT1 Function 0h FALSE 1h A AND B 2h A AND B 3h A 4h A AND B 5h B 6h A XOR B 7h A OR B 8h A NOR B 9h A XNOR B Ah B Bh A OR B Ch A Dh A OR B Eh A NAND B Fh TRUE 3 0 LUT0 3 0 Select logic function for LUT0 Function 0h FALSE 1h A AND B 2h A AND B 3h A 4h A AND B 5h B 6h A XOR B 7h A OR B 8h A NOR B 9h A XNOR B Ah B Bh A OR B Ch A Dh A OR B Eh A NAND B Fh...

Page 155: ...chapter 7 4 LUT3 3 0 Select logic function for LUT3 Function 0h FALSE 1h A AND B 2h A AND B 3h A 4h A AND B 5h B 6h A XOR B 7h A OR B 8h A NOR B 9h A XNOR B Ah B Bh A OR B Ch A Dh A OR B Eh A NAND B Fh TRUE 3 0 LUT2 3 0 Select logic function for LUT2 Function 0h FALSE 1h A AND B 2h A AND B 3h A 4h A AND B 5h B 6h A XOR B 7h A OR B 8h A NOR B 9h A XNOR B Ah B Bh A OR B Ch A Dh A OR B Eh A NAND B Fh...

Page 156: ...N 0 Disable Row s LUT1 output to global output 1 Enable Row s LUT1 output to GOE 5 4 GOE1EN 0 Disable Row s LUT1 output to global output 1 Enable Row s LUT1 output to GOE 1 3 GOO4EN 0 Disable Row s LUT0 output to global output 1 Enable Row s LUT0 output to GOO 4 2 GOO0EN 0 Disable Row s LUT0 output to global output 1 Enable Row s LUT0 output to GOO 0 1 GOE4EN 0 Disable Row s LUT0 output to global ...

Page 157: ...N 0 Disable Row s LUT3 output to global output 1 Enable Row s LUT3 output to GOE 7 4 GOE3EN 0 Disable Row s LUT3 output to global output 1 Enable Row s LUT3 output to GOE 3 3 GOO6EN 0 Disable Row s LUT2 output to global output 1 Enable Row s LUT2 output to GOO 6 2 GOO2EN 0 Disable Row s LUT2 output to global output 1 Enable Row s LUT2 output to GOO 2 1 GOE6EN 0 Disable Row s LUT2 output to global ...

Page 158: ... 5 Bus Error IE Bus Error Interrupt Enable 0 Disabled 1 Enabled An interrupt is generated on the detection of a Bus Error 4 Stop IE Stop Interrupt Enable 0 Disabled 1 Enabled An interrupt is generated on the detection of a Stop Condition 3 2 Clock Rate 1 0 00b 100K Standard Mode 01b 400K Fast Mode 10b 50K Standard Mode 11b Reserved 1 Enable Master Writing a 0 to both the Enable Master and Enable S...

Page 159: ...it position It is never cleared by the hardware 1 A Stop condition is detected 4 ACK Acknowledge Out This bit is automatically cleared by hardware on a Byte Complete event 0 NACK the last received byte 1 ACK the last received byte 3 Address 0 This status bit must be cleared by firmware with write of 0 to the bit position 1 The received byte is a slave address 2 Transmit Transmit bit is set by firm...

Page 160: ...d transmit receive since last cleared by firmware Any Start detect or a write to the Start or Restart generate bits when operating in Master mode also clears the bit Transmit Mode 1 Eight bits of data have been transmitted and an ACK or NACK has been received Receive Mode 1 Eight bits of data have been received ...

Page 161: ...is read only for received data and write only for transmitted data For additional information refer to the Register Definitions on page 298 in the I2C chapter 7 0 Data 7 0 Read received data or write data to transmit Individual Register Names and Addresses 0 D8h I2C_DR 0 D8h 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name Data 7 0 Bit Name Description ...

Page 162: ...etected from any bus master 1 When a Start condition is detected from any bus master 2 Master Mode This bit is set cleared by hardware when the device is operating as a master 0 Stop condition detected generated by this device 1 Start condition detected generated by this device 1 Restart Gen This bit is cleared by hardware when the Restart generation is complete 0 Restart generation complete 1 Gen...

Page 163: ... 3 Read 1 Posted interrupt present for Variable Clock 3 Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for Variable Clock 3 6 Sleep Read 0 No posted interrupt for sleep timer Read 1 Posted interrupt present for sleep timer Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Writ...

Page 164: ...ed interrupt for analog columns Read 1 Posted interrupt present for analog columns Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for analog columns 0 V Monitor Read 0 No posted interrupt for supply voltage monitor Read 1 Posted interrupt present for supply voltage monitor Write 0 AND...

Page 165: ...chapter 3 DCB03 Digital Communications Block type B row 0 position 3 Read 0 No posted interrupt Read 1 Posted interrupt present Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt 2 DCB02 Digital Communications Block type B row 0 position 2 Read 0 No posted interrupt Read 1 Posted interrup...

Page 166: ... interrupt is posted in the inter rupt controller In the table above note that reserved bits are grayed table cells and are not described in the bit description section below Reserved bits should always be written with a value of 0 For additional information refer to the Register Def initions on page 64 in the Interrupt Controller chapter 0 I2C Read 0 No posted interrupt for I2C Read 1 Posted inte...

Page 167: ...g a pending interrupt In the table above note that reserved bits are grayed table cells and are not described in the bit description section below Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 64 in the Interrupt Controller chapter 7 ENSWINT 0 Disable software interrupts 1 Enable software interrupts 0 I2C 0 Mask I2C in...

Page 168: ...ion Reserved bits should always be writ ten with a value of 0 For additional information refer to the Register Definitions on page 64 in the Interrupt Controller chap ter 7 VC3 0 Mask VC3 interrupt 1 Unmask VC3 interrupt 6 Sleep 0 Mask sleep interrupt 1 Unmask sleep interrupt 5 GPIO 0 Mask GPIO interrupt 1 Unmask GPIO interrupt 4 SAR8 ADC 0 Mask analog interrupt SAR8 ADC 1 Unmask SAR8 ADC interrup...

Page 169: ...described in the bit description section Reserved bits should always be writ ten with a value of 0 For additional information refer to the Register Definitions on page 64 in the Interrupt Controller chap ter 3 DCB03 0 Mask Digital Communication Block row 0 position 3 off 1 Unmask Digital Communication Block row 0 position 3 2 DCB02 0 Mask Digital Communication Block row 0 position 2 off 1 Unmask D...

Page 170: ...r additional information refer to the Register Definitions on page 64 in the Interrupt Controller chapter 7 0 Pending Interrupt 7 0 Read Returns vector for highest priority pending interrupt Write Clears all pending and posted interrupts Individual Register Names and Addresses 0 E2h INT_VC 0 E2h 7 6 5 4 3 2 1 0 Access POR RC 00 Bit Name Pending Interrupt 7 0 Bit Name Description ...

Page 171: ...the sleep timer For additional information refer to the Register Definitions on page 33 in the Sleep and Watchdog chapter 7 0 WDSL_Clear 7 0 Any write clears the watchdog timer A write of 38h clears both the watchdog and sleep timers Individual Register Names and Addresses 0 E3h RES_WDT 0 E3h 7 6 5 4 3 2 1 0 Access POR W 00 Bit Name WDSL_Clear 7 0 Bit Name Description ...

Page 172: ...isters DEC_DH and DEC_DL are not For additional information refer to the Register Definitions on page 293 in the Decimator chapter 7 0 Data High Byte 7 0 Read Returns the high byte of the decimator Write Clears the 16 bit accumulator values Either the DEC_DH or DEC_DL register may be writ ten to clear the accumulators that is it is not necessary to write both Individual Register Names and Addresse...

Page 173: ...isters DEC_DH and DEC_DL are not For additional information refer to the Register Definitions on page 293 in the Decimator chapter 7 0 Data Low Byte 7 0 Read Returns the low byte of the decimator Write Clears the 16 bit accumulator values Either the DEC_DH or DEC_DL register may be writ ten to clear the accumulators that is it is not necessary to write both Individual Register Names and Addresses ...

Page 174: ...ck number that does not exist in a specific PSoC should be considered reserved For example a PSoC device with 2 rows may choose any block numbered 0x or 1x but not a block numbered 2x or 3x ICLKS0 0b Digital block 02 1b Digital block 12 2 1 DCOL 1 0 Decimator Column Source Selects the analog comparator column as a data source for the decima tor 00b Analog Column 0 01b Analog Column 1 10b Reserved ...

Page 175: ...onsidered reserved For example a PSoC device with 2 rows may choose any block num bered 0x or 1x but not a block numbered 2x or 3x 5 3 ICLKSx ICLKS3 ICLKS2 ICLKS1 cont 000b Digital block 02 001b Digital block 12 010b Digital block 01 011b Digital block 11 100b Digital block 00 101b Digital block 10 110b Digital block 03 111b Digital block 13 2 0 DCLKSx Decimator Latch Select Along with DCLKS0 in D...

Page 176: ...he signed 8 bit multiplier in the PSoC MAC For additional information refer to the Register Definitions on page 287 in the Multiply Accumulate chapter 7 0 Data 7 0 X multiplicand for MAC 8 bit multiplier Individual Register Names and Addresses 0 E8h MUL0_X 0 E8h 7 6 5 4 3 2 1 0 Access POR W XX Bit Name Data 7 0 Bit Name Description ...

Page 177: ...he signed 8 bit multiplier in the PSoC MAC For additional information refer to the Register Definitions on page 287 in the Multiply Accumulate chapter 7 0 Data 7 0 Y multiplicand for MAC 8 bit multiplier Individual Register Names and Addresses 0 E9h MUL0_Y 0 E9h 7 6 5 4 3 2 1 0 Access POR W XX Bit Name Data 7 0 Bit Name Description ...

Page 178: ...ant byte of the 16 bit product For additional information refer to the Register Definitions on page 287 in the Multiply Accumulate chapter 7 0 Data 7 0 High byte of MAC multiplier 16 bit product Individual Register Names and Addresses 0 EAh MUL0_DH 0 EAh 7 6 5 4 3 2 1 0 Access POR R XX Bit Name Data 7 0 Bit Name Description ...

Page 179: ...ant byte of the 16 bit product For additional information refer to the Register Definitions on page 287 in the Multiply Accumulate chapter 7 0 Data 7 0 Low byte of MAC multiplier 16 bit product Individual Register Names and Addresses 0 EBh MUL0_DL 0 EBh 7 6 5 4 3 2 1 0 Access POR R XX Bit Name Data 7 0 Bit Name Description ...

Page 180: ...er Definitions on page 287 in the Multiply Accumulate chapter 7 0 Data 7 0 Read Returns the 2nd byte of the 32 bit accumulated value The 2nd byte is next to the least sig nificant byte for the accumulated value Write X multiplicand for the MAC 16 bit multiply and 32 bit accumulator Individual Register Names and Addresses 0 ECh MAC0_X ACC0_DR1 0 ECh 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name Data 7 ...

Page 181: ...egister Definitions on page 287 in the Multiply Accumulate chapter 7 0 Data 7 0 Read Returns the 1st byte of the 32 bit accumulated value The 1st byte is the least significant byte for the accumulated value Write Y multiplicand for the MAC 16 bit multiply and 32 bit accumulate Individual Register Names and Addresses 0 EDh MAC0_Y ACC0_DR0 0 EDh 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name Data 7 0 Bit...

Page 182: ...efinitions on page 287 in the Multiply Accumulate chapter 7 0 Data 7 0 Read Returns the 4th byte of the 32 bit accumulated value The 4th byte is the most significant byte MSB for the accumulated value Write Writing any value to this address clears all four bytes of the Accumulator Individual Register Names and Addresses 0 EEh MAC0_CL0 ACC0_DR3 0 EEh 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name Data 7...

Page 183: ...finitions on page 287 in the Multiply Accumulate chapter 7 0 Data 7 0 Read Returns the 3rd byte of the 32 bit accumulated value The 3rd byte is next to most signifi cant byte for the accumulated value Write Writing any value to this address clears all four bytes of the Accumulator Individual Register Names and Addresses 0 EFh MAC0_CL1 ACC0_DR2 0 EFh 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name Data 7...

Page 184: ...cified by the stack page pointer STK_PP 10b Direct Address mode instructions are referred to the RAM page specified by the current page pointer CUR_PP Indexed Address mode instructions are referred to the RAM page specified by the index page pointer IDX_PP 11b Direct Address mode instructions are referred to the RAM page specified by the current page pointer CUR_PP Indexed Address mode instruction...

Page 185: ...the CY8C24533 CY8C23533 CY8C23433 CY8C24633 CY8C24x23 and CY8C22x13 PSoC devices 7 IRESS This bit is read only 0 Boot phase only executed once 1 Boot phase occurred multiple times 3 ECO EXW ECO Exists Written 1 The ECO Exists Written bit has been written with a 1 or 0 and is now locked 0 The ECO Exists Written bit has never been written in User mode 2 ECO EX ECO Exists write once see the explanati...

Page 186: ...s discouraged as the Flag register is now readable at address x F7h read only 5 WDRS Watchdog Reset Status This bit may not be set by user code however it may be cleared by writing it with a 0 0 No Watchdog Reset occurred 1 Watchdog Reset occurred 4 PORS Power On Reset Status This bit may not be set by user code however it may be cleared by writing it with a 0 0 Power On Reset has not occurred and...

Page 187: ... bit 2 in PRT0DM2 The three bits from the three registers are treated as a group These are referred to as DM2 DM1 and DM0 or together as DM 2 0 All Drive mode bits are shown in the sub table below 210 refers to the combination in order of bits in a given bit position however this register only controls the least significant bit LSb of the Drive mode For additional information refer to the Register...

Page 188: ... as DM2 DM1 and DM0 or together as DM 2 0 All Drive mode bits are shown in the sub table below 210 refers to the combination in order of bits in a given bit position however this register only controls the middle bit of the Drive mode For additional information refer to the Register Definitions on page 8 in the GPIO chapter 7 0 Drive Mode 1 7 0 Bit 1 of the Drive mode for each of 8 port pins for a...

Page 189: ...egister bits that control the Interrupt mode for that pin for example Bit 2 in PRT0IC0 and bit 2 in PRT0IC1 The two bits from the two registers are treated as a group In the sub table below 0 refers to the combination in order of bits in a given position one bit from PRTxIC1 and one bit from PRTxIC0 For additional information refer to the Register Definitions on page 8 in the GPIO chapter 7 0 Inte...

Page 190: ...egister bits that control the Interrupt mode for that pin for example Bit 2 in PRT0IC0 and bit 2 in PRT0IC1 The two bits from the two registers are treated as a group In the sub table below 1 refers to the combination in order of bits in a given position one bit from PRTxIC1 and one bit from PRTxIC0 For additional information refer to the Register Definitions on page 8 in the GPIO chapter 7 0 Inte...

Page 191: ...cteristics of your PSoC device some addresses may not be available For additional information refer to the Register Definitions on page 187 in the Digital Blocks chapter 7 Data Invert 0 Data input is non inverted 1 Data input is inverted 6 BCEN Enable Primary Function Output to drive the broadcast net 0 Disable 1 Enable 5 End Single 0 Block is not the end of a chained function or the function is n...

Page 192: ...rection 0 Receiver 1 Transmitter Mode 1 signifies the Interrupt Type 0 Interrupt on TX Reg Empty 1 Interrupt on TX Complete SPI Mode 0 signifies the Type 0 Master 1 Slave Mode 1 signifies the Interrupt Type 0 Interrupt on TX Reg Empty 1 Interrupt on SPI Complete 2 0 Function 2 0 000b Timer chainable 001b Counter chainable 010b CRCPRS chainable 011b Reserved 100b Dead Band 101b UART DCBxx blocks on...

Page 193: ...esents Prefix mn Suf fix where m row index n column index Therefore DCB12IN is a digital communication register for a digital PSoC block in row 1 column 2 Depending on the digital row characteristics of your PSoC device some addresses may not be available For additional information refer to the Register Definitions on page 187 in the Digital Blocks chapter 7 4 Data Input 3 0 0h Low 0 1h High 1 2h ...

Page 194: ...ck Input 3 0 0h Clock disabled low 1h VC3 2h Row broadcast net 3h Previous block primary output low for DBB00 4h SYSCLKX2 5h VC1 6h VC2 7h CLK32K 8h Row output 0 9h Row output 1 Ah Row output 2 Bh Row output 3 Ch Row input 0 Dh Row input 1 Eh Row input 2 Fh Row input 3 ...

Page 195: ...igital row characteristics of your PSoC device some addresses may not be available For addi tional information refer to the Register Definitions on page 187 in the Digital Blocks chapter 7 6 AUXCLK 00b No sync 16 to 1 clock mux output 01b Synchronize Output of 16 to 1 clock mux to SYSCLK 10b Synchronize Output of 16 to 1 clock mux to SYSCLKX2 11b SYSCLK Directly connect SYSCLK to block clock input...

Page 196: ...rce for SS_ Input if AUXEN 1 cont 00b Force SS_ Active 01b Reserved 10b Reserved 11b Reserved 2 OUTEN Enable Primary Function Output Driver 0 Disabled 1 Enabled 1 0 Output Select 1 0 Row Output Select for Primary Function Output 00b Row Output 0 01b Row Output 1 10b Row Output 2 11b Row Output 3 ...

Page 197: ...on section Reserved bits should always be written with a value of 0 For additional information refer to the Register Defini tions on page 227 in the Analog Interface chapter 3 2 AColumn1 1 0 Clock selection for column 1 00b Variable Clock 1 VC1 01b Variable Clock 2 VC2 10b Analog Clock 0 ACLK0 11b Analog Clock 1 ACLK1 1 0 AColumn0 1 0 Clock selection for column 0 00b Variable Clock 1 VC1 01b Varia...

Page 198: ...e for Analog Clock 1 000b Digital Basic Block 00 001b Digital Basic Block 01 010b Digital Communication Block 02 011b Digital Communication Block 03 100b Digital Basic Block 10 101b Digital Basic Block 11 110b Digital Communication Block 12 111b Digital Communication Block 13 2 0 ACLK0 2 0 Select the clocking source for Analog Clock 0 000b Digital Basic Block 00 001b Digital Basic Block 01 010b Di...

Page 199: ...among P0 6 4 2 0 1 Set column 1 input to column 0 input mux output 1 Column selects among P0 7 5 3 1 5 ABUF1EN Enables the analog output buffer for Analog Column 1 Pin P0 5 0 Disable analog output buffer 1 Enable analog output buffer 3 ABUF0EN Enables the analog output buffer for Analog Column 0 Pin P0 3 1 Column AGND 0 Disable analog output buffer 1 Enable analog output buffer 1 Bypass Connects t...

Page 200: ...ional information refer to the Register Definitions on page 227 in the Analog Interface chapter 2 0 AMOD0 2 0 Analog modulation control signal selection for column 0 000b Zero off 001b Global Output Bus even bus bit 1 GOE 1 010b Global Output Bus even bus bit 0 GOE 0 011b Row 0 Broadcast Bus 100b Analog Column Comparator 0 101b Analog Column Comparator 1 110b Analog Column Comparator 2 111b Analog...

Page 201: ...ation refer to the Register Definitions on page 227 in the Analog Interface chapter 2 0 AMOD1 2 0 Analog modulation control signal selection for column 1 000b Zero off 001b Global Output Bus even bus bit 1 GOE 1 010b Global Output Bus even bus bit 0 GOE 0 011b Row 0 Broadcast Bus 100b Analog Column Comparator 0 101b Analog Column Comparator 1 110b Analog Column Comparator 2 111b Analog Column Comp...

Page 202: ... 0h FALSE 1h A AND B 2h A AND B 3h A 4h A AND B 5h B 6h A XOR B 7h A OR B 8h A NOR B 9h A XNOR B Ah B Bh A OR B Ch A Dh A OR B Eh A NAND B Fh TRUE 3 0 LUT0 3 0 Select 1 of 16 logic functions for output of comparator bus 0 Function 0h FALSE 1h A AND B 2h A AND B 3h A 4h A AND B 5h B 6h A XOR B 7h A OR B 8h A NOR B 9h A XNOR B Ah B Bh A OR B Ch A Dh A OR B Eh A NAND B Fh TRUE Individual Register Nam...

Page 203: ...el high 1 DCB03 DR0 is driving the channel high Bit 6 0 DCB03 DR0 is not driving the channel low 1 DCB03 DR0 is driving the channel low 5 4 DCB02_HL 1 0 Bit 5 0 DCB02 DR0 is not driving the channel high 1 DCB02 DR0 is driving the channel high Bit 4 0 DCB02 DR0 is not driving the channel low 1 DCB02 DR0 is driving the channel low 3 2 DBB01_HL 1 0 Bit 3 0 DBB01 DR0 is not driving the channel high 1 ...

Page 204: ...nabled a selected digital block is enabled and the selected digital block s DR0 data is equal to the data of this register For additional information refer to the Register Definitions on page 266 in the SAR8 ADC Block chapter 7 0 CMP_L 7 0 The comparator data for low channel trigger Individual Register Names and Addresses 1 A9h SARADC_TRCL 1 A9h 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name CMP_L 7 0 ...

Page 205: ...enabled a selected digital block is enabled and the selected digital block s DR0 data is equal to the data of this register For additional information refer to the Register Definitions on page 266 in the SAR8 ADC Block chapter 7 0 CMP_H 7 0 The comparator data for high channel trigger Individual Register Names and Addresses 1 AAh SARADC_TRCH 1 AAh 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name CMP_H 7 ...

Page 206: ... when read out This feature does not affect the raw data in ADC raw results register It only affects the data read out to the MCU 2 0 ADC Clock 2 0 000 ADC clock is SYSCLK 001 ADC clock is SYSCLK 2 010 ADC clock is SYSCLK 4 011 ADC clock is SYSCLK 8 100 ADC clock is SYSCLK 16 101 ADC clock is SYSCLK 32 010 ADC clock is SYSCLK 64 ADC sample rate is ADC clock divided by 8 and its conversion time is ...

Page 207: ...erence voltage generation control It is write only in Test mode For additional information refer to the Register Definitions on page 266 in the SAR8 ADC Block chapter 7 0 DA_L 7 0 The low byte control for reference voltage Individual Register Names and Addresses 1 ACh SARADC_LCR 1 ACh 7 6 5 4 3 2 1 0 Access POR RW 00 Bit Name DA_L 7 0 Bits Name Description ...

Page 208: ...s not drive GOO 5 1 GIO 5 drives its value on to GOO 5 4 GIONOUT4 0 GIO 4 does not drive GOO 4 1 GIO 4 drives its value on to GOO 4 3 GIONOUT3 0 GIO 3 does not drive GOO 3 1 GIO 3 drives its value on to GOO 3 2 GIONOUT2 0 GIO 2 does not drive GOO 2 1 GIO 2 drives its value on to GOO 2 1 GIONOUT1 0 GIO 1 does not drive GOO 1 1 GIO 1 drives its value on to GOO 1 0 GIONOUT0 0 GIO 0 does not drive GOO...

Page 209: ...s not drive GOE 5 1 GIE 5 drives its value on to GOE 5 4 GIENOUT4 0 GIE 4 does not drive GOE 4 1 GIE 4 drives its value on to GOE 4 3 GIENOUT3 0 GIE 3 does not drive GOE 3 1 GIE 3 drives its value on to GOE 3 2 GIENOUT2 0 GIE 2 does not drive GOE 2 1 GIE 2 drives its value on to GOE 2 1 GIENOUT1 0 GIE 1 does not drive GOE 1 1 GIE 1 drives its value on to GOE 1 0 GIENOUT0 0 GIE 0 does not drive GOE...

Page 210: ...s not drive GIO 5 1 GOO 5 drives its value on to GIO 5 4 GOOUTIN4 0 GOO 4 does not drive GIO 4 1 GOO 4 drives its value on to GIO 4 3 GOOUTIN3 0 GOO 3 does not drive GIO 3 1 GOO 3 drives its value on to GIO 3 2 GOOUTIN2 0 GOO 2 does not drive GIO 2 1 GOO 2 drives its value on to GIO 2 1 GOOUTIN1 0 GOO 1 does not drive GIO 1 1 GOO 1 drives its value on to GIO 1 0 GOOUTIN0 0 GOO 0 does not drive GIO...

Page 211: ...es not drive GIE 5 1 GOE 5 drives its value on to GIE 5 4 GOEUTIN4 0 GOE 4 does not drive GIE 4 1 GOE 4 drives its value on to GIE 4 3 GOEUTIN3 0 GOE 3 does not drive GIE 3 1 GOE 3 drives its value on to GIE 3 2 GOEUTIN2 0 GOE 2 does not drive GIE 2 1 GOE 2 drives its value on to GIE 2 1 GOEUTIN1 0 GOE 1 does not drive GIE 1 1 GOE 1 drives its value on to GIE 1 0 GOEUTIN0 0 GOE 0 does not drive GI...

Page 212: ...net 1 The VC2 clock is driven onto GOE 5 4 VC1 0 The VC1 clock is not driven onto a global net 1 The VC1 clock is driven onto GOE 4 3 SYSCLKX2 0 The 2 times system clock is not driven onto a global net 1 The 2 times system clock is driven onto GOE 3 2 SYSCLK 0 The system clock is not driven onto a global net 1 The system clock is driven onto GOE 2 1 CLK24M 0 The 24 MHz clock is not driven onto a g...

Page 213: ...scription section below Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 279 in the Digital Clocks chapter 1 0 VC3 Input Select 1 0 Selects the clocking source for the VC3 Clock Divider 00b SYSCLK 01b VC1 10b VC2 11b SYSCLKX2 Individual Register Names and Addresses 1 DEh OSC_CR4 1 DEh 7 6 5 4 3 2 1 0 Access POR RW 0 Bit N...

Page 214: ...requency output from the VC3 Clock Divider is one eighth the input frequency For additional information refer to the Register Definitions on page 279 in the Digital Clocks chapter 7 0 VC3 Divider 7 0 Refer to the OSC_CR4 register 00h Input Clock 01h Input Clock 2 02h Input Clock 3 03h Input Clock 4 FCh Input Clock 253 FDh Input Clock 254 FEh Input Clock 255 FFh Input Clock 256 Individual Register ...

Page 215: ...ms 8 Hz 11b 1 s 1 Hz 2 0 CPU Speed 2 0 These bits set the CPU clock speed based on the system clock SYSCLK SYSCLK is 24 MHz by default but it can optionally be set to 6 MHz on some PSoC devices see the Architectural Description on page 15 or driven from an external clock 6 MHz IMO 24 MHz IMO External Clock 000b 750 kHz 3 MHz EXTCLK 8 001b 1 5 MHz 6 MHz EXTCLK 4 010b 3 MHz 12 MHz EXTCLK 2 011b 6 MH...

Page 216: ...al Clock 0h 24 OSC_CR1 7 4 1 1 EXTCLK OSC_CR1 7 4 1 1 1h 24 OSC_CR1 7 4 1 2 EXTCLK OSC_CR1 7 4 1 2 2h 24 OSC_CR1 7 4 1 3 EXTCLK OSC_CR1 7 4 1 3 3h 24 OSC_CR1 7 4 1 4 EXTCLK OSC_CR1 7 4 1 4 4h 24 OSC_CR1 7 4 1 5 EXTCLK OSC_CR1 7 4 1 5 5h 24 OSC_CR1 7 4 1 6 EXTCLK OSC_CR1 7 4 1 6 6h 24 OSC_CR1 7 4 1 7 EXTCLK OSC_CR1 7 4 1 7 7h 24 OSC_CR1 7 4 1 8 EXTCLK OSC_CR1 7 4 1 8 8h 24 OSC_CR1 7 4 1 9 EXTCLK OS...

Page 217: ...on page 279 in the Digital Clocks chapter 7 PLLGAIN Phase locked loop gain 0 Recommended value normal gain 1 Reduced gain to make PLL more tolerant to noisy or jittery crystal input 2 EXTCLKEN External clock mode enable 0 Disabled Operate from internal main oscillator 1 Enabled Operate from clock supplied at port P1 4 1 RSVD Reserved bit This bit should always be 0 0 SYSCLKX2DIS 48 MHz clock sourc...

Page 218: ...R level for 2 4 V or 3V operation refer to the PSoC device data sheet 01b POR level for 3 0V or 4 5V operation refer to the PSoC device data sheet 10b POR level for 4 75V operation 11b Reserved 3 LVDTBEN Enables reset of CPU speed register by LVD comparator output 0 Disables CPU speed throttle back 1 Enables CPU speed throttle back 2 0 VM 2 0 Sets the LVD and pump levels per the DC electrical spec...

Page 219: ...egister Definitions on page 320 in the POR and LVD chapter 2 PUMP Read state of pump comparator 0 Vdd is above trip point 1 Vdd is below trip point 1 LVD Reads state of LVD comparator 0 Vdd is above LVD trip point 1 Vdd is below LVD trip point 0 PPOR Reads state of Precision POR comparator only useful with PPOR reset disabled with PORLEV 1 0 in VLT_CR register set to 11b 0 Vdd is above PPOR trip v...

Page 220: ...formation refer to the Register Definitions on page 16 in the Internal Main Oscillator chapter 7 0 Trim 7 0 The value of this register is used to trim the Internal Main Oscillator Its value is set to the best value for the device during boot The value of these bits should not be changed 00h Lowest frequency setting 01h 7Fh 80h Design center setting 81h FEh FFh Highest frequency setting Individual ...

Page 221: ... Definitions on page 19 in the Internal Low Speed Oscillator chapter 5 4 Bias Trim 1 0 The value of this register is used to trim the Internal Low Speed Oscillator Its value is set to the device specific best value during boot The value of these bits should not be changed 00b Medium bias 01b Maximum bias recommended 10b Minimum bias 11b Intermediate Bias About 15 higher than the minimum bias 3 0 F...

Page 222: ...GNDBYP If set an external bypass capacitor on AGND may be connected to Port 2 4 0 Disable 1 Enable 5 4 TC 1 0 The value of these bits is used to trim the temperature coefficient Their value is set to the best value for the device during boot The value of these bits should not be changed 3 0 V 3 0 The value of these bits is used to trim the bandgap reference Their value is set to the best value for...

Page 223: ...table cells and are not described in the bit description section below Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 23 in the External Crystal Oscillator ECO chapter 7 6 PSSDC 1 0 Sleep duty cycle Controls the ratios in numbers of 32 768 kHz clock periods of on time versus off time for PORLVD Bandgap reference and psp...

Page 224: ...bit description section below Reserved bits should always be written with a value of 0 For additional information refer to the Supervisory ROM SROM chapter on page 45 1 0 Bank 1 0 Selects the active Flash bank for supervisory operations No affect in User mode 00b Flash Bank 0 01b Flash Bank 1 10b Flash Bank 2 11b Flash Bank 3 Individual Register Names and Addresses 1 FAh FLS_PR1 1 FAh 7 6 5 4 3 2 ...

Page 225: ...C23533 CY8C23433CY8C24633 PSoC devices The following table lists the resources available for the CY8C24533 CY8C23533 CY8C23433CY8C24633 and related PSoC devices While reading the digital system section keep in mind the number of digital rows that are in the CY8C24533 CY8C23533 CY8C23433CY8C24633 is 1 DIGITAL SYSTEM To System Bus Digital Clocks From Core Digital PSoC Block Array To Analog System 8 ...

Page 226: ...0 RW 00 x B3h RDI0LT0 LUT1 3 0 LUT0 3 0 RW 00 x B4h RDI0LT1 LUT3 3 0 LUT2 3 0 RW 00 x B5h RDI0RO0 GOO5EN GOO1EN GOE5EN GOE1EN GOO4EN GOO0EN GOE4EN GOE0EN RW 00 x B6h RDI0RO1 GOO7EN GOO3EN GOE7EN GOE3EN GOO6EN GOO2EN GOE6EN GOE2EN RW 00 DIGITAL BLOCK REGISTERS page 187 Digital Block Data and Control Registers page 187 0 20h DBB00DR0 Data 7 0 00 0 21h DBB00DR1 Data 7 0 W 00 0 22h DBB00DR2 Data 7 0 0...

Page 227: ...N AUX IO Select 1 0 OUTEN Output Select 1 0 RW 00 Digital Block Interrupt Mask Registers page 187 0 E1h INT_MSK1 DCB03 DCB02 DBB01 DBB00 RW 00 LEGEND x An x before the comma in the address field indicates that this register can be read or written to no matter what bank is used R Read register or bit s Access is bit specific Refer to the Register Details chapter on page 47 for additional informatio...

Page 228: ...164 Document 001 20559 Rev D Section D Digital System ...

Page 229: ...es with even in their name connect to all even numbered ports There are two ends to the global digital interconnect core signals and port pins An end may be configured as a source or a destination For example a GPIO pin may be configured to drive a global input or receive a global output and drive it to the package pin Globals cannot loop through a GPIO Currently there are two types of core sig na...

Page 230: ...in the 28 pin PSoC device Figure 14 1 Global Interconnect Block Diagram for a 28 up to 32 Pin Package Table 14 1 28 up to 32 Pin Global Bus to Port Mapping Global Bus Ports GIO 7 0 GOO 7 0 P1 GIE 7 0 GOE 7 0 P0 P2 P0 6 GO GI P0 4 GO GI P0 2 GO GI P0 7 GO GI P0 5 GO GI P0 3 GO GI P0 1 GO GI P0 0 GO GI P1 6 GO GI P1 4 GO GI P1 2 GO GI P1 7 GO GI P1 5 GO GI P1 3 GO GI P1 1 GO GI P1 0 GO GI GIE 0 GIE ...

Page 231: ...the PSoC devices There are a total of 16 bits that control the ability of global inputs to drive global outputs These bits are in the GDI_x_IN registers Table 14 2 enumerates the meaning of each bit position in either of the GDI_O_IN or GDI_E_IN registers For additional information refer to the GDI_O_IN register on page 144 and the GDI_E_IN register on page 145 Add Name Bit 7 Bit 6 Bit 5 Bit 4 Bit...

Page 232: ...tes the meaning of each bit position in either of the GDI_O_OU or GDI_E_OU registers For additional information refer to the GDI_O_OU register on page 146 and the GDI_E_OU register on page 147 Add Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1 D2h GDI_O_OU GOOUTIN7 GOOUTIN6 GOOUTIN5 GOOUTIN4 GOOUTIN3 GOOUTIN2 GOOUTIN1 GOOUTIN0 RW 00 1 D3h GDI_E_OU GOEUTIN7 GOEUTIN6 GOEUTIN5 GOEUTIN4...

Page 233: ...hat make a row s position unique are explained as follows Register Address Rows and the blocks within them need to have unique register addresses Interrupt Priority Each digital PSoC block has its own interrupt priority and vector A row s position in the array determines the relative priority of the digital PSoC blocks within the row The lower the row number the higher the interrupt priority and t...

Page 234: ...170 Document 001 20559 Rev D Array Digital Interconnect ADI ...

Page 235: ...This figure shows the connections between digital blocks within a row Only the signals that pass outside the gray background box in Figure 16 1 are shown at the next level of hierarchy in Figure 16 2 on page 172 In Figure 16 2 the detailed view shown in Figure 16 1 of the four PSoC block grouping has been replaced by the box in the center of the figure labeled 4 PSoC Block Grouping The rest of the...

Page 236: ... 3 GOE 7 L3 Digital PSoC Block Row GIE 0 GlO 4 GlO 0 GlE 4 RI 0 GIE 1 GlO 5 GlO 1 GlE 5 RI 1 GIE 2 GlO 6 GlO 2 GlE 6 RI 2 GIE 3 GlO 7 GlO 3 GlE 7 RI 3 BCROW 0 BCROW DB 7 0 DBI TPB FPB AUX 3 0 DATA 15 0 CLK 15 0 TNB FNB RO 3 0 INT 3 0 BCROW 4 PSoC Block Grouping High VC3 Broadcast BC Previous Block CLK SYSCLKX2 VC1 VC2 CLK32K RO 3 0 RI 3 0 ACMP 3 0 Low Previous Block Data RI 3 RO 3 RI 2 RO 2 RI 1 R...

Page 237: ... holder for the row index Table 16 1 lists the meaning for each mux s four possible settings Bits 1 and 0 RI0 1 0 These bits control the input mux for row 0 For additional information refer to the RDIxRI register on page 87 16 2 2 RDIxSYN Register The Row Digital Interconnect Synchronization Register RDIxSYN is used to control the input synchronization The RDIxRI Register and the RDIxSYN Register ...

Page 238: ...the DxBxxFN Registers on page 193 Bit 3 IS3 This bit controls the A input of LUT 3 Bit 2 IS2 This bit controls the A input of LUT 2 Bit 1 IS1 This bit controls the A input of LUT 1 Bit 0 IS0 This bit controls the A input of LUT 0 For additional information refer to the RDIxIS register on page 89 Add Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access x B2h RDI0IS BCSEL 1 0 IS3 IS2 IS1 IS0 ...

Page 239: ...ut column of a two input logic truth table Table 16 4 lists seven examples of the relationship between the LUT s output column for a truth table and the LUTx 3 0 configuration bits Figure 16 3 on page 174 presents an example of LUT configuration Bits 7 to 4 LUTx 3 0 These configuration bits are for a row output LUT Bits 3 to 0 LUTx 3 0 These configuration bits are for a row output LUT For addition...

Page 240: ...ration bits enable the tri state buffers that connect to the Global Output Even lines for LUT 0 For additional information refer to the RDIxRO0 register on page 92 16 2 5 2 RDIxRO1 Register Bits 7 to 4 GOxxEN These configuration bits enable the tri state buffers that connect to the Global Output Even lines for LUT 3 Bits 3 to 0 GOxxEN These configuration bits enable the tri state buffers that conn...

Page 241: ...ons may be used by configuring an individual PSoC block or chaining several PSoC blocks together to form functions that are greater than 8 bits Digital communications PSoC blocks have two additional functions master or slave SPI and a full duplex UART Each digital PSoC block s function is independent of all other PSoC blocks Up to seven registers are used to deter mine the function and state of a ...

Page 242: ...1 and VC2 or SYSCLK for setting see Table 17 1 2 If the clock input is derived from SYSCLKX2 resynchro nize to SYSCLKX2 For example VC3 clocked by SYSCLKX2 or other digital blocks clocked by SYSCLKX2 for setting see Table 17 1 3 Choose direct SYSCLK for clocking directly off of SYS CLK for setting see Table 17 1 4 Choose direct SYSCLKX2 select SYSCLKX2 in the Clock Input field of the DxBxxIN regis...

Page 243: ...equivalent to a hard ware capture A CPU read of DR0 with the timer enabled triggers the same capture mechanism The hardware and software capture mechanisms are OR ed in the capture cir cuitry Since the capture circuitry is positive edge sensitive during an interval where the hardware capture input is high a software capture is masked and does not occur The timer also implements a compare function ...

Page 244: ...ources interrupt on terminal count TC and interrupt on compare may be selected in Mode bit 0 of the function register Interrupt on Terminal Count The positive edge of ter minal count auxiliary output generates an interrupt for this block The timing of the interrupt follows the TC pulse width setting in the control register Interrupt on Compare The positive edge of compare primary output generates ...

Page 245: ...al block in the same row Since the kill is asynchronous the digital block output must be resynchronized through a row input before using it as a digital block input 17 1 8 2 Block Interrupt The dead band block has one fixed interrupt source which is the Phase 1 primary output clock When the KILL signal is asserted the interrupt follows the same behavior of the Phase 1 output with respect to the va...

Page 246: ...back taps as input into the least significant bit In the modular method there is an XOR operation imple mented between each register bit and each tap point enables the XOR with the MSb for that given bit The CRCPRS function implements the modular approach These are equivalent methods However there is a conver sion that should be understood If tables are specified in simple register format then a c...

Page 247: ...om the DATA input MISO and output to the pri mary output F1 MOSI DR1 is the TX Buffer register and DR2 is the RX Buffer register The SPI protocol requires data to be registered at the device input on the opposite edge of the clock that operates the output shifter An additional register RXD at the input to the DR0 shift register has been implemented for this pur pose This register stores received d...

Page 248: ...to the shift register The SPIS function derives all clocking from the SCLK input typically an external SPI master This means that the mas ter must initiate all transmissions For example to read a byte from the SPIS the master must send a byte There are 4 control bits and 4 status bits in the control regis ter that provide for PSoC device interfacing and synchroni zation In the SPIS there is an add...

Page 249: ...e to the TX Buffer register DR1 initiates a transmis sion and an additional byte can be buffered in this register while transmission is in progress An additional feature of the transmitter function is that a clock generated with set up and hold time for the data bits only is output to the auxiliary output This allows connection to a CRC generator or other digital blocks 17 1 13 2 Usability Excepti...

Page 250: ...the DR2 RX Buffer register An additional feature of the receiver function is that input data RXD and the synchronized clock are passed to the primary output and auxiliary output respectively This allows connection to a CRC generator or other digital block 17 1 13 5 Usability Exceptions The following are usability exceptions for the asynchronous receiver function 1 The RXD input must be resynchroni...

Page 251: ... reference timing diagrams associated with the digital block registers see Timing Diagrams on page 198 For a complete table of digital block registers refer to the Summary Table of the Digital Registers on page 162 Data and Control Registers The following table summarizes the Data and Control registers by function type for the digital blocks Table 17 4 Digital Block Data and Control Register Defin...

Page 252: ...e contents of DR0 to DR2 This transfer only occurs in the addressed block When enabled a read of DR0 returns 00h to the data bus and synchronously transfers the contents of DR0 to DR2 It oper ates simultaneously on the byte addressed and all higher bytes in a multi block timer Note that when the hardware capture input is high the read of DR0 software capture is masked and does not occur The hardwa...

Page 253: ...is 24 MHz or below this register may be written to at any time but the period is only reloaded into DR0 in the clock following a TC If the block frequency is 48 MHz the terminal count or compare interrupt should be used to synchronize the new period register write otherwise the counter could be incorrectly loaded DR2 Compare Read write register DR2 functions as a compare register When enabled the ...

Page 254: ...the seed value directly into DR0 When enabled DR2 may be written to at any time The value written is used in the compare function When enabled the compare output is computed using the compare type set in the function register mode bits between DR0 and DR2 The result of the compare is output to the auxiliary output When disabled a read of DR0 transfers the contents of DR0 into DR2 This feature can ...

Page 255: ... Full status in the control CR0 register is set A read from this register DR2 clears the RX Reg Full status bit in the control register Table 17 11 Transmitter Data Register Descriptions Name Function Description DR0 Shifter Not readable or writeable During normal operation DR0 implements a shift register for shifting out serial data DR1 TX Buffer Write only register If no transmission is in progr...

Page 256: ...e is enabled the output of this register is substituted for the PWM reference This register may be toggled by user firm ware to generate PHI1 and PHI2 output clock with the programmed dead time The options for Bit Bang mode are as follows 0 Function uses the previous clock primary output as the input reference 1 Function uses the bit bang clock register as the input reference CRCPRS There are two ...

Page 257: ...Bit 7 Data Invert This bit inverts the selected data input Bit 6 BCEN This bit enables the primary output of the block to drive the row broadcast block The BCEN bit is set independently in each block and therefore care must be taken to ensure that only one BCEN bit in a given row is enabled However if any of the blocks in a given row have the BCEN bit set the input that allows the broadcast net fr...

Page 258: ...bits in the timer block control the interrupt type and the compare type Counter The mode bits in the counter block control the Interrupt type and the compare type same as the timer function Dead Band The mode bits are encoded as the kill type See the table titled Dead Band KILL Options on page 181 for an explanation of kill options CRCPRS The mode bits are encoded to determine the compare type SPI...

Page 259: ... The dead band reference input does not use the auxiliary input mux It is hardwired to be the primary output of the previous block For CRC computation the input data is a serial data stream synchronized to the clock For PRS mode this input should be forced to logic 0 For additional information refer to the DxBxxIN register on page 129 Add Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access...

Page 260: ...XCLK All digital block clock inputs must be resynchronized The digital blocks have numerous selec tions for clocking In addition to the system clocks including VC1 VC2 and VC3 clocks generated by other digital blocks may be selected through row or global interconnect To maintain the integrity of block timing all clocks are resyn chronized at the input to the digital block The two AUXCLK bits are u...

Page 261: ...e and therefore routing SS_ in through a row input is not required Bit 2 OUTEN This bit enables the primary output to be driven onto the selected row output Output Select 1 0 These two bits indicate which of the four row outputs the primary output is driven onto For additional information refer to the DxBxxOU register on page 131 Table 17 18 AUXCLK Bit Selections Code Description Usage 00 Bypass U...

Page 262: ...next higher block to count once for every terminal count TC of all lower blocks The terminal count out of a given block becomes the termi nal count in of the next least significant block in the chain The terminal count output indicates that the block and all higher blocks are at 00h count The terminal count in termi nal count out chaining signals provide a way for the lower blocks to know when the...

Page 263: ...enable must have at least one 24 MHz cycle of set up time to the block clock This is ensured if internal or synchronized external inputs are used As shown in Figure 17 8 when the data input is negated counting is disabled and the count is 00h the TC output stays low When the data input goes high again the TC occurs on the following input clock When the block is dis abled the clock is immediately g...

Page 264: ...asserted Reference High Phase 1 Reference Low Phase 2 The minimum dead time occurs with a period value of 00h and that dead time is one clock cycle Figure 17 9 Basic Dead Band Timing 17 3 3 1 Changing the PWM Duty Cycle Under normal circumstances the dead band period is less than the minimum PWM high or low time As an example consider Figure 17 10 where the low of the PWM is four clocks the dead b...

Page 265: ...n KILL is asserted high the internal state is held in reset and the initial dead band period is reloaded into the counter While KILL is held high incoming PWM reference edges are ignored When KILL is negated the next incoming PWM refer ence edge restarts dead band processing See Figure 17 13 2 Asynchronous Restart Mode When KILL is asserted high the internal state is not affected When KILL is nega...

Page 266: ...icates the relationship of the clock to the data When the clock phase is 0 it means that the data is registered as an input on the leading edge of the clock and the next data is output on the trailing edge of the clock When the clock phase is 1 it means that the next data is output on the leading edge of the clock and that data is reg istered as an input on the trailing edge of the clock Clock pol...

Page 267: ...a byte to transmit when TX Reg Empty status is true If no transmission is currently in progress the data is loaded into the shifter and the transmission is initiated The TX Reg Empty status is asserted again and the user is allowed to write the next byte to be transmitted to the TX Buffer regis ter After the last bit is output if TX Buffer data is available with one half clock set up time to the n...

Page 268: ...ed when eight bits of data and clock have been sent In modes 0 and 1 this occurs one half cycle after RX Reg Full is set because in these modes data is latched on the leading edge of the clock and there is an additional one half cycle remaining to complete that clock In modes 2 and 3 this occurs at the same edge that the receive data is latched This signal may be used to read the received byte or ...

Page 269: ...ress SCLK Mode 1 SCLK Mode 0 SS Transfer in Progress Transfer in Progress MODE 2 3 Phase 1 Output on leading edge Input on trailing edge SCLK Polarity 0 Mode 2 MOSI MISO SCLK Polarity 1 Mode 3 7 6 5 4 3 2 1 0 SS_ TX REG EMPTY RX REG FULL SPI COMPLETE OVERRUN Overrun occurs one half cycle before the last bit is received Last bit of byte is received All clocks and data for this byte completed TX Buf...

Page 270: ...he MISO output reverts to its idle 1 state All internal states are reset including CR0 sta tus to their configuration specific reset state except for DR0 DR1 and DR2 which are unaffected Normal Operation Typical timing for an SPIS transfer is shown in Figure 17 20 and Figure 17 21 If the SPIS is pri marily being used as a receiver the RX Reg Full polling only or SPI Complete polling or interrupt s...

Page 271: ... from the TX Buffer register All modes use the following mechanism 1 If there is no transfer in progress 2 if the shifter is empty and 3 if data is available in the TX Buffer register the byte is loaded into the shifter The only difference between the modes is that the definition of transfer in progress is slightly different between modes 0 and 1 and modes 2 and 3 Figure 17 22 illustrates TX data ...

Page 272: ...ith the received byte Loading the shifter by the leading edge of the clock has the effect of providing the required one half clock set up time as the data is latched into the receiver on the trailing edge of the SCLK in these modes Figure 17 23 Mode 2 and 3 Transfer in Progress SCLK Mode1 SS Toggled on a MessageBasis SS Toggled on EachByte SCLK Mode1 SCLK Mode0 SS TransferinProgress TransferinProg...

Page 273: ...ding CR0 status to their configuration specific reset state except for DR0 DR1 and DR2 which are unaffected Transmit Operation Transmission is initiated with a write to the TX Buffer register DR1 The CPU write to this regis ter is required to have one half bit clock set up time for the data to be recognized at the next positive internal bit clock edge As shown in Figure 17 24 once the set up time ...

Page 274: ...es one subject to the timing The default interrupt in the transmitter is tied to TX Reg Empty However an initial interrupt is not generated when the block is enabled The user must write an initial byte to the TX Buffer register That byte must be transferred into the shifter before interrupts generated from the TX Reg Empty status bit are enabled This prevents an interrupt from occur ring immediate...

Page 275: ...new data byte reception The RX Reg Full status bit as well as error status is also set at the STOP sample point To facilitate connection to other digital blocks the RXD input is passed directly to the RXDOUT primary output The SCLK auxiliary output has an SPI mode 3 clock associated with the data bits for mode 3 timing see Figure 17 27 Dur ing the mark idle and framing bits the SCLK output is high...

Page 276: ... s In this case the new maximum offset is 4 35 ms 42 ns 4 35 ms x 5 or 4 95 At slower baud rates this value gets closer to the theoretical maximum of five percent Status Generation There are five status bits in a receiver block RX Reg Full RX Active Framing Error Overrun and Parity Error All status bits except RX Active and Overrun are set synchronously on the STOP bit sample point RX Reg Full ind...

Page 277: ...rrun status is set one half cycle before RX Reg Full This means that although the new data is not available the previous data has been overwritten because the latch was opened Parity Error status indicates that resulting parity calculation on the received byte does not match the value of the parity bit that was transmitted This status is set on the sample point of the STOP signal Status Clear On R...

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Page 279: ... drivers are discussed in detail within the PSoC Core section in the Analog Output Drivers chapter on page 13 PSoC Analog System Interpreting the Analog Documentation Information in this section covers the CY8C24533 CY8C23533 CY8C23433CY8C24633 PSoC device The following table lists the resources available for the CY8C24533 CY8C23533 CY8C23433CY8C24633 and related PSoC devices While reading the ana...

Page 280: ...alog blocks in a column Only one block in a column can actively drive this bus at any one time with the user having control of this output through register settings This is the only ana log output that can be driven directly to a pin 2 The comparator bus CBUS is a digital bus resource that is shared by all of the analog blocks in a column Only one block in a column can be actively driving this bus...

Page 281: ... 1 61h CLK_CR1 SHDIS ACLK1 2 0 ACLK0 2 0 RW 00 1 63h AMD_CR0 AMOD0 2 0 RW 00 1 66h AMD_CR1 AMOD1 2 0 RW 00 1 67h ALT_CR0 LUT1 3 0 LUT0 3 0 RW 00 ANALOG INPUT CONFIGURATION REGISTERS page 243 0 60h AMX_IN ACI1 1 0 ACI0 1 0 RW 00 1 62h ABF_CR0 ACol1Mux ABUF1EN ABUF0EN Bypass PWR RW 00 ANALOG REFERENCE REGISTER page 246 0 63h ARF_CR HBE REF 2 0 PWR 2 0 RW 00 CONTINUOUS TIME PSoC BLOCK REGISTERS page ...

Page 282: ... CMP_L 7 0 RW 00 1 AAh SARADC_TRC H CMP_H 7 0 RW 00 1 ABh SARADC_CR2 Test Enable Free Run Scale Size 2 0 ADC Clock 2 0 0 1 ACh SARADC_LCR DA_L 7 0 RW 00 LEGEND x An x before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used Access is bit specific Refer to the Register Details chapter on page 47 for additional information R Read re...

Page 283: ...C23433CY8C24633 devices Analog Column 0 for this device includes one CT Continuous Time block and the SAR8 ADC block rather than the two standard SC Switched Capacitor blocks Figure 18 1 Analog Comparator Bus Slice Latch CMP CBUS Driver Transparent PHI1 or PHI2 Latch PHI2 BYPASS CLDIS CMP_CR1 7 4 To Col i 1 LUT From Col i 1 IGEN 1 0 Incremental Gate One per Column From Digital Blocks Destinations ...

Page 284: ...2 the latch retains the value on the comparator bus during the high to low transition of PHI2 The CMP_CR0 register is described in the CMP_CR0 Reg ister on page 227 There is also an option to force the latch in each column into a transparent mode by setting bits in the CMP_CR1 register As shown in Figure 18 1 the comparator bus output is gated by the primary output of a selected digital block This...

Page 285: ... input frequency to be in phase Writing these registers should be avoided during critical analog processing as col umn clocks are all re initialized and thus a discontinuity in PHI1 PHI2 clocking occurs Figure 18 3 Column Clock Resynchronize on an IO Write 18 1 4 Decimator and Incremental ADC Interface The Decimator and Incremental ADC Interface provides hardware support and signal routing for ana...

Page 286: ...e of PHI1 the CPU stall is released allowing the IO write to be performed at the destination analog register This mode synchronizes the IO write action to perform at the optimum point in the analog cycle at the expense of CPU bandwidth Figure 18 4 shows the timing for this operation Figure 18 4 Synchronized Write to a DAC Register As an alternative to stalling the source for the analog col umn int...

Page 287: ...e overrides two bits of the data To correct the previous bit guess based on the current comparator value To set the next guess next least significant bit The CPU latches this SAR modified data OR s it with 0 no CPU modification and writes it back to the DAC register A counter in the SAR hardware is used to decode which bits are being operated on in each cycle In this way the capabil ity of the CPU...

Page 288: ...6 bits of the SAR algorithm Typically the user initializesx this register to 6 When these bits are any value other than 0 an IOR command to an SC block is assumed to be part of a SAR sequence Assuming the comparator bus output is programmed for col umn 0 a typical firmware sequence is as follows mov reg ASY_CR 60h SAR count value 6 Sign 0 Col 0 or reg ASD11CR0 0 Check sign set bit 4 or reg ASD11CR...

Page 289: ...the SIGN bit should be from the result in the MS block and write it to the LS block Then the SAR count value should be set to 5 instead of 6 to skip the sign bit check 2 An interesting property of the SAR algorithm is that the resulting voltage at the summing node after the first 6 steps MS block processing is going to be the same polarity above or below AGND as the input voltage The reason for th...

Page 290: ...stall is released the IO read completes and is immediately followed by an IO write In this sequence of events the DAC register is written with the new value within a few CPU clocks after PHI1 The rising edge of PHI1 is also the optimal time to write the DAC register for maximum settling time The timing from the positive edge of PHI1 to the start of the IO write is 4 5 clocks which at 24 MHz is 189...

Page 291: ...terface Stall ing on page 222 The SAR hardware accelerator is a block of specialized hardware designed to sequence the SAR algorithm for effi cient analog to digital conversion A SAR ADC is imple mented conceptually with a DAC of the desired precision and a comparator This functionality is configured from one or more PSoC blocks For each conversion the firmware ini tializes the ASY_CR register and...

Page 292: ...ging When this bit is set any write to an SC block register is stalled until the rising edge of the next PHI1 clock phase for the column associated with the SC block address The stall ing operation is implemented by suspending the CPU clock No CPU activity occurs during the stall including interrupt processing Therefore the effect of stalling on CPU through put must be considered For additional in...

Page 293: ...e resources with DCLKS0 in this register and DCLKS3 DCLKS2 and DCLKS1 in the DEC_CR1 reg ister For additional information refer to the DEC_CR0 register on page 110 18 4 5 DEC_CR1 Register The Decimator Control Register 1 DEC_CR1 is used to configure the decimator prior to using it Bit 7 ECNT The ECNT bit is a mode bit that controls the operation of the decimator hardware block By default the decim...

Page 294: ...2 During PHI1 and for the first half of PHI2 the output bus floats at the last voltage to which it was driven This forms a sample and hold operation using the output bus and its associated capacitance This design prevents the output bus from being perturbed by the inter mediate states of the SC operation often a reset state for PHI1 and settling to the valid state during PHI2 The following are the...

Page 295: ...buses two global buses and one broadcast bus The default for this function is zero or off Bits 2 to 0 AMOD1 2 0 These bits control the selection of the MODBITs for analog column 1 For additional information refer to the AMD_CR1 register on page 137 18 4 10 ALT_CR0 Register The Analog LUT Control Register 0 ALT_CR0 is used to select the logic function A one of 16 look up table LUT is applied to the...

Page 296: ...232 Document 001 20559 Rev D Analog Interface ...

Page 297: ...he analog multiplexer mux connections for the various PSoC devices which vary depending on column availability Figure 19 1 displays the various analog arrays for the CY8C24533 CY8C23533 CY8C23433CY8C24633 PSoC device family Analog column 1 has 3 analog blocks associ ated with it Analog column 0 has 1 analog block and 1 SAR8 ADC block associated with it In the figures throughout this chapter shadin...

Page 298: ...nding NMux select line values for the data in the NMux portion of the register The call out names in the figure show nets selected for each NMux value For one column PSoC devices the figure view is expanded in a circular area to the left of the main diagram where black call outs and arrows signify exclusive one column functional ity and gray call outs and arrows signify commonality with four and t...

Page 299: ...PMux select line values for the data in the PMux portion of the register The call out names in the figure show nets selected for each PMux value For one column PSoC devices the figure view is expanded in a circular area to the left of the main diagram where black call outs and arrows signify exclusive one column functional ity and gray call outs and arrows signify commonality with four and two col...

Page 300: ...x con nections that are selected by the combination of the RBot Mux bits ACB0xCR0 bits 1 and 0 and the INSAMP bit ACB0xCR3 bit 1 For example the RBotMux selects a connection to AGND if the INSAMP bit is low and the RBot Mux bits are 01b This is shown in the figure as the logic statement For one column PSoC devices the figure view is expanded in a circular area to the left of the main diagram where...

Page 301: ...mbers in Figure 19 5 which are associated with each arrow are the corresponding AMux select line values for the data in the ACMux portion of the register The call out names in the figure show nets selected for each AMux value For one column PSoC devices the figure view is expanded in a circular area to the left of the main diagram where black call outs and arrows signify exclusive one column funct...

Page 302: ...tions are used in the Switched Capacitor PSoC blocks These blocks are named ASC10 and ASC21 The CMux connections are described in detail in the ASCxxCR1 register on page 84 bits ACMux 2 0 The num bers in the figure which are associated with each arrow are the corresponding CMux select line values for the data in the CMux portion of the register The call out names in the figure show nets selected f...

Page 303: ...dedicated comparator bus asso ciated with it Every analog PSoC block has a comparator output that can drive out on this bus However the compara tor output from only one analog block in a column can be actively driving the comparator bus for that column at any one time Refer to the Analog Comparator Bus Interface on page 220 in the Analog Interface chapter for more informa tion 19 2 Temperature Sen...

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Page 305: ...re 20 1 Figure 20 2 presents a more detailed view of the analog col umn configuration for the CY8C24533 CY8C23533 CY8C23433CY8C24633 PSoC devices along with analog driver and pin specifics The input multiplexer mux maps device inputs package pins to analog array columns based on bit values in the AMX_IN and ABF_CR0 registers Refer to the analog block diagram on the following page to view the vario...

Page 306: ... Figure 20 2 Two Column PSoC Analog Pin Block Diagram ACOL1MUX P0 6 P0 4 P0 2 P0 0 P2 2 P2 0 ACB00 ACB01 ASD11 ASC21 Array P2 6 P2 4 RefIn AGNDIn P0 7 P0 5 P0 3 P0 1 P2 3 P2 1 28 and Higher Pin Part 20 Pin Part 8 Pin Part Array Input Configuration AGNDIn RefIn Bandgap RefHi RefLo AGND Reference Generators Microcontroller Interface Address Bus Data Bus Etc Interface to Digital System ACI0 1 0 ACI1 ...

Page 307: ...tly into the Switched Capacitor PSoC blocks For additional information refer to the AMX_IN register on page 64 20 2 2 ABF_CR0 Register The Analog Output Buffer Control Register 0 ABF_CR0 controls analog input muxes from Port 0 and the output buf fer amplifiers that drive column outputs to device pins Bit 7 ACol1MUX A mux selects the output of column 0 input mux or column 1 input mux When set this ...

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Page 309: ...all offset volt age between buffered analog grounds RefHi and RefLo sig nals are generated buffered and routed to the analog blocks RefHi and RefLo are used to set the conversion range that is span of analog to digital ADC and digital to analog DAC converters RefHi and RefLo can also be used to set thresholds in comparators the two column PSoC devices The reference array supplies voltage to all bl...

Page 310: ...pamps have a faster slew rate but slightly less voltage swing and higher power Bits 5 to 3 REF 2 0 REF AGND RefHi and RefLo sets the analog array reference control selecting specific combi nations of voltage for analog ground and references Many of these reference voltages are based on the precision inter nal reference a silicon bandgap operating at 1 30 volts This reference has good thermal stabi...

Page 311: ...V P2 4 P2 6 1 2 V User Adjustable Example P2 4 2 2V and P2 6 1 0V 010b Vdd 2 2 5 V 1 65 V Vdd 5 0 V 3 3 V Vss 0 0 V 0 0 V 5 0 V System 3 3 V System 011b 2 Vbg 2 6 V 3 Vbg 3 9 V 1 Vbg 1 3 V Not for 3 3 V Systems 100b 2 Vbg 2 6 V 2 Vbg P2 6 3 6 V 2 Vbg P2 6 1 6 V P26 Vdd 2 6 Example P2 6 1 0V 101b P2 4 2 2 V P2 4 Vbg 3 5 V P2 4 Vbg 0 9 V User Adjustable Example P2 4 2 2V 1 3 P2 4 Vdd 1 3 110b Vbg 1 ...

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Page 313: ...hat determine the sig nal topology inside the block There is also a precision resistor string located in the feedback path of the opamp which is controlled by register bit settings The block also contains a low power comparator connected to the same inputs and outputs as the main amplifier This comparator is useful for providing a digital compare output in low power sleep modes when the main ampli...

Page 314: ...Diagram RBotMux INSAMP Block Inputs Block Inputs PMux AGND AGND ABUS NMux RefHi RefLo PWR CompCap SCBLK RTapMux GOUT LOUT Gain RESISTOR MATRIX Port Input GIN FB ABUS AnalogBus OUT CBUS Gain TestMux RefHi AGND PMuxOut RefLo Vdd RTopMux CMOUT LPCMPEN Latch CBUS Driver Transparent PHI1 or PHI2 EXGAIN ...

Page 315: ...ake a three opamp instrumentation amplifier see Figure 22 3 The three opamp instrumentation amplifier handles a larger common mode input range but takes more resources Bit 2 CMOUT and bit 1 INSAMP control switches are involved in the three opamp instrumentation amplifier Bit 3 LPCMPEN Each continuous time block has a low power comparator connected in parallel with the block s main opamp comparator...

Page 316: ...xxCR0 RtapMux 3 0 For RtapMux values from 02h through 15h the EXGAIN bit has no effect on which tap is selected See the ACBxxCR0 register for details The EXGAIN bit enables additional resistor tap selections for RtapMux 01h and RtapMux 00h see Figure 22 4 For additional information refer to the ACBxxCR3 register on page 73 Figure 22 4 CT Block in Gain Configuration NON RB RA INV RA RB PHI1 1st CT ...

Page 317: ...nalogBus This bit controls the analog output bus ABUS A CMOS switch connects the opamp output to the analog bus Bit 6 CompBus This bit controls a tri state buffer that drives the comparator logic If no block in the analog column is driving the comparator bus it is driven low externally to the blocks Bits 5 to 3 NMux 2 0 These bits control the multiplexing of inputs to the inverting input of the op...

Page 318: ...is con nected to the ABUS for that particular continuous time block If the TMUXEN bit is low then none of the test mux inputs are connected to the ABUS regardless of the value of Test Mux 1 0 Bits 3 and 2 TextMux 1 0 These bits select which signal is connected to the analog bus Bits 1 and 0 PWR 1 0 Power is encoded to select one of three power levels or power down off The blocks power up in the of...

Page 319: ...ngs in control registers set the capacitor topology inside the block A group of muxes are used for the signal processing and switch synchronously to clocks PHI1 and PHI2 with behavior that is modified by con trol register settings There is also an analog comparator that converts the opamp output relative to the local analog ground into a digital signal There are two types of Analog Switched Capaci...

Page 320: ...s 1 FSW0 1 AutoZero BMuxSC BQTA P ABU S C Inputs CCa p BCa p ACa p 0 1 30 31 C FCa p 16 32 C 2 AutoZero 1 AutoZero 2 AutoZero FSW1 Powe r AnalogBus 2B 1 ASign ARefMux OU T 2 1 RefHi RefLo AGND ACMux A Inputs B Inputs CBUS CBUS Driver 0 1 30 31 C 0 1 30 31 C Modulation Inputs Mod Bit Control 2 2 1 Comparator ...

Page 321: ...labeled BQTAP in the figure above The local connection of BQTAP is between horizontal neighboring SC blocks within an analog bi col umn Since the input of SC Block C ASCxx has this addi tional switched capacitor it is configured for the input stage of such a switched capacitor bi quad filter When followed by an SC Block D ASDxx integrator this combination of blocks can be used to provide a full un...

Page 322: ...to be read or written The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that follow Reserved bits should always be written with a value of 0 Figure 23 3 applies to the ACap BCap and CCap functionality for the capacitor registers The XCap field is used to store the binary encoded value for capacitor X where X can be A ACap B BCap...

Page 323: ... intermediate states of the SC operation often a reset state for PHI1 and settling to the valid state during PHI2 The following are the exceptions 1 If the ClockPhase bit in CR0 for the SC block in ques tion is set to 1 then the output is enabled for the whole of PHI2 2 If the SHDIS signal is set in bit 6 of the Analog Clock Source Control register then sample and hold operation is disabled for al...

Page 324: ... the ABUS Bit 6 CompBus This bit controls the output to the column comparator bus CBUS Note that if the CBUS is not driven by anything in the column it is pulled low The comparator output is evaluated on the rising edge of internal PHI1 and is latched so it is available during internal PHI2 Bit 5 AutoZero This bit controls the shorting of the output to the inverting input of the opamp When shorted...

Page 325: ...toZero bit determines the state of the switch If the AutoZero bit is 0 the switch is enabled at all times If the AutoZero bit is 1 the switch is enabled only when the internal PHI2 is high Bit 4 FSW0 This bit is used to control a switch in the inte grator capacitor path It connects the output of the opamp to analog ground Bits 3 and 2 BMuxSC 1 0 These bits control the muxing to the input of the B ...

Page 326: ...y the intermediate states of the SC operation often a reset state for PHI1 and settling to the valid state during PHI2 The following are the exceptions 1 If the ClockPhase bit in CR0 for the SC block in ques tion is set to 1 then the output is enabled for the whole of PHI2 2 If the SHDIS signal is set in bit 6 of the Analog Clock Select register then sample and hold operation is dis abled for all ...

Page 327: ...put to the column comparator bus CBUS Note that if the CBUS is not driven by anything in the column it is pulled low The comparator output is evaluated on the rising edge of internal PHI1 and is latched so it is available during internal PHI2 Bit 5 AutoZero This bit controls the shorting of the output to the inverting input of the opamp When shorted the opamp is basically a follower The output is ...

Page 328: ... FSW0 This bit is used to control a switch in the inte grator capacitor path It connects the output of the opamp to analog ground Bit 3 BSW This bit is used to control switching in the B branch If disabled the B capacitor branch is a continuous time branch like the C branch of the SC A Block If enabled then on internal PHI1 both ends of the cap are switched to analog ground On internal PHI2 one en...

Page 329: ... the analog voltage levels from up to ten different sources The analog input channels of the ADC are available at Port 0 24 1 1 Features Successive approximation functionality support 8 bit resolution Eight primary input analog channels and two inside ana log channels which come from two CT blocks Support for right side scale feature when reading con version result data Scale size is programmed as...

Page 330: ...is not ready or the conversion data has already been read out Writing 1 to Start Busy bit automatically clears the bit to 0 When 1 ADC has newest conversion data which has never been read out Bit 1 Start Busy When 0 ADC has finished the opera tion If firmware writes a 1 to this bit it means that firmware triggers the ADC to perform the sample and conversion from the next system clock cycle If this...

Page 331: ...omparator in cases when the PWM is 16 bits Note that the digital block enable signal is also used in auto trigger generation We separate the 16 bit comparator into two 8 bit channels H channel and L channel for maximum flexibility Every digital block can drive both channels at the same time but each channel can only be driven by one digital block The lower digital blocks have higher priority than ...

Page 332: ...etting the SARADC_TRCL register triggers the ADC start conversion at any point during one PWM cycle You can also select two adjacent blocks as auto align trigger source to align with a 16 bit PWM timer or counter Be sure that the block you select is the same block you place the user module with which you want the ADC to align Bits 7 and 6 DCB03_HL 1 0 Bits 5 and 4 DCB02_HL 1 0 Bits 3 and 2 DBB01_H...

Page 333: ...RCL reg ister on page 140 24 2 6 SARADC_TRCH Register The SAR8 ADC High Channel Comparator Data Register SARADC_TRCH is the ADC auto align trigger comparator data register A trigger occurs when the high channel trigger is enabled a selected digital block is enabled and the selected digital block s DR0 data is equal to the data of this register Bits 7 to 0 CMP_H 7 0 The comparator data for high cha...

Page 334: ..._CR2 regis ter on page 142 24 2 8 SARADC_LCR Register The SAR8 ADC Reference Voltage Generator Control Reg ister SARADC_LCR is the ADC DA register used for refer ence voltage generation control It is write only in Test mode Bits 7 to 0 DA_L 7 0 The low byte control for reference voltage For additional information refer to the SARADC_LCR regis ter on page 143 Add Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 ...

Page 335: ...tecture of the PSoC s system resources Each component of the figure is discussed at length in this section CY8C24533 CY8C23533 CY8C23433CY8C24633 PSoC Device System Resources Interpreting the System Resources Documentation The following table lists the resources available for the CY8C24533 CY8C23533 CY8C23433CY8C24633 and related PSoC devices SYSTEM BUS Multiply Accumulate MAC I2C Internal Voltage...

Page 336: ..._CR3 VC3 Divider 7 0 RW 00 1 E0h OSC_CR0 32k Select PLL Mode No Buzz Sleep 1 0 CPU Speed 2 0 RW 00 1 E1h OSC_CR1 VC1 Divider 3 0 VC2 Divider 3 0 RW 00 1 E2h OSC_CR2 PLLGAIN EXTCLKEN RSVD SYSCLKX2 DIS RW 00 MULTIPLY ACCUMULATE MAC REGISTERS page 287 0 E8h MUL0_X Data 7 0 W XX 0 E9h MUL0_Y Data 7 0 W XX 0 EAh MUL0_DH Data 7 0 R XX 0 EBh MUL0_DL Data 7 0 R XX 0 ECh MAC0_X ACC0_DR 1 Data 7 0 RW 00 0 E...

Page 337: ...XX POR AND LVD REGISTERS page 320 1 E3h VLT_CR SMP PORLEV 1 0 LVDTBEN VM 2 0 RW 00 1 E4h VLT_CMP PUMP LVD PPOR R 00 LEGEND X The value after power on reset is unknown C Clearable register or bits R Read register or bit s W Write register or bit s Access is bit specific Refer to the Register Details chapter on page 47 for additional information Summary Table of the System Resource Registers continu...

Page 338: ...274 Document 001 20559 Rev D Section F System Resources ...

Page 339: ...MHz See the Architectural Description on page 15 in the Internal Main Oscillator chapter for more information The IMO is discussed in detail in the chapter Internal Main Oscillator IMO on page 15 25 1 2 Internal Low Speed Oscillator The Internal Low Speed Oscillator ILO is always on unless the device is operating off an external crystal The ILO is available as a general clock but is also the clock...

Page 340: ...ster PLL Lock Enable P1 1 P1 0 ILO Trim Register Vdd CLK32K SYSCLK VC3 SYSCLKX2 VC3SEL Clock Doubler 732 EXTCLK P1 4 EXTCLK Input OSC_CR0 7 ILO_TR 7 0 ECO Trim Register ECO_TR 7 0 IMO_TR 7 0 OSC_CR0 6 Vdd OSC_CR2 2 Clock Divider OSC_CR0 2 0 Clock Divider OSC_CR1 7 4 Clock Divider OSC_CR1 3 0 Clock Divider OSC_CR3 7 0 Sleep Clock Divider OSC_CR0 4 3 26 29 212 215 SYSCLKX2 Disable OSC_CR2 0 Slow IMO...

Page 341: ...is selected the SYSCLKX2 signal is still available and serves as a doubler for whatever frequency is input on the external clock pin Following the specification for the external clock input ensures that the internal circuitry of the digital PSoC blocks which is clocked by SYSCLKX2 meets timing requirements However since the doubled clock is generated from both edges of the input clock clock jitter...

Page 342: ...ice distinctions that apply to the digital clocks are listed as follows In PSoC devices with a part number of CY8C24x23 or CY8C22x13 bit 7 of the OSC_GO_EN register is reserved However in PSoC devices with a part number of CY8C24533 CY8C23533 CY8C23433CY8C24633 or CY8C24x23A bit 7 is not reserved CPUCLK IMO Extenal Clock SYSCLK IOW_ EXTCLK bit IMO is deselected External clock is selected CPUCLK IM...

Page 343: ... This bit controls the VC3 clock interrupt status Bits 6 to 0 The INT_CLR0 register holds bits that are used by several different resources For a full discussion of the INT_CLR0 register see the INT_CLRx Registers in the Interrupt Controller chapter on page 61 For additional information refer to the INT_CLR0 register on page 99 25 3 2 INT_MSK0 Register The Interrupt Mask Register 0 INT_MSK0 is use...

Page 344: ... onto GOE 1 Bit 0 CLK32K This bit enables the driving of the 32 kHz clock onto GOE 0 For additional information refer to the OSC_GO_EN regis ter on page 148 25 3 4 OSC_CR4 Register The Oscillator Control Register 4 OSC_CR4 selects the input clock to variable clock 3 VC3 Bits 1 and 0 VC3 Input Select 1 0 The VC3 clock net is the only clock net with the ability to generate an interrupt The input clo...

Page 345: ...nerates pending interrupts every number of clock periods equal to the VC3 divider register value plus one Therefore if the VC3 divider register s value is 05h divide by 6 an interrupt occurs every six periods of the VC3 s input clock Another example is if the divider value is 00h divide by one an interrupt is generated on every period of the VC3 clock The VC3 mask bit only controls the ability of ...

Page 346: ...C_CR0 register There are eight frequencies generated from a power of two divide circuit which are selected by a 3 bit code At any given time the CPU 8 to 1 clock mux is selecting one of the available frequencies which is resyn chronized to the 24 MHz master clock at the output Regardless of the CPU speed bit s setting if the actual CPU speed is greater than 12 MHz the 24 MHz operating requirements...

Page 347: ...ddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 1 E1h OSC_CR 1 VC1 Divider 3 0 VC2 Divider 3 0 RW 00 Table 25 6 OSC_CR1 7 4 Bits VC1 Divider Value Bits Divider Source Clock Internal Main Oscillator at 24 MHz External Clock 0h 24 MHz EXTCLK 1 1h 12 MHz EXTCLK 2 2h 8 MHz EXTCLK 3 3h 6 MHz EXTCLK 4 4h 4 8 MHz EXTCLK 5 5h 4 MHz EXTCLK 6 6h 3 43 MHz EXTCLK 7 7h 3 MHz EXTCLK 8 8h 2 67...

Page 348: ...al clock tree SYSCLK which drives most PSoC device clocking functions All external and internal signals including the 32 kHz clock whether derived from the internal low speed oscillator ILO or the crystal oscillator are synchronized to this clock source If an external clock is enabled PLL mode should be off The external clock input is located on port P1 4 When using this input the pin Drive mode s...

Page 349: ...ctural Description The MAC is a register based system resource Its only inter face is the system bus therefore there are no special clocks or enables that are required to be sourced from digi tal or analog PSoC blocks The architectural presentation of the MAC is illustrated in Figure 26 1 Figure 26 1 MAC Block Diagram Table 26 1 MAC Availability PSoC Part Number Number of MAC Blocks CY8C24x23A 1 C...

Page 350: ...is implemented on top of simple multiplication When using the MAC to accu mulate the products of successive multiplications two 8 bit signed values are used for input The product of the multipli cation is accumulated as a 32 bit signed value The user has the choice to either cause a multiply accumu late function to take place or a multiply only function The user selects which operation is performe...

Page 351: ...C When these write only registers are written the product of the written value and the current value of the MULx_X registers are calculated For additional information refer to the MULx_X register on page 112 26 3 2 MULx_Y Register The Multiply Input Y Register MULx_Y is one of two multi plicand registers for the signed 8 bit multiplier in the PSoC MAC Bits 7 to 0 Data 7 0 The multiply Y MULx_Y reg...

Page 352: ...cond byte of the accumulated value Bits 7 to 0 Data 7 0 This register performs two distinct functions therefore two names are used to refer to the same address When the address is written a multiply oper ation with accumulation is performed The multiply accumu late X MACx_X register is one of the two multiplicand registers for the signed 8 bit multiply with accumulate opera tion When this register...

Page 353: ...inct functions therefore two names are used to refer to the same address When the address is written with any value all 32 bits of the accumulator are reset to zero When this address is read the accumulator s data register 3 is read This register holds the most significant of four bytes used to hold the accumulator s value For additional information refer to the MACx_CL0 ACCx_DR3 register on page ...

Page 354: ...290 Document 001 20559 Rev D Multiply Accumulate MAC ...

Page 355: ...es Because the input signal is a discrete time signal the weight of each encoding is analogous to the area under the signal for that instant in time Therefore to integrate the signal the sum of the weights must be calculated over a period of time When the decimator is configured as a single integrator this is exactly what happens For each period of the input clock the current area integral value i...

Page 356: ...re three 16 bit internal registers in the type 1 decimator A0 A1 and AB see Figure 27 3 The A0 register is used to store the 16 bit sum from the Data A0 calculation The A1 register is used to store the 16 bit sum from the A0 A1 calcula tion The AB register is the register that is readable by way of the data bus The A0 and A1 registers are not accessible from outside the block Figure 27 3 Decimator...

Page 357: ...r the decimator s value Note that this register does not reset to 00h The DEC_DH register resets to an indetermi nate value For additional information refer to the DEC_DH register on page 108 27 2 2 DEC_DL Register The Decimator Data Low Register DEC_DL is a dual pur pose register used to read the low byte of the decimator s output or clear the decimator Bits 7 to 0 Data Low Byte 7 0 When the regi...

Page 358: ...ht digital blocks depending on the PSoC device resources with DCLKS0 in this register and DCLKS3 DCLKS2 and DCLKS1 in the DEC_CR1 reg ister For additional information refer to the DEC_CR0 register on page 110 27 2 4 DEC_CR1 Register The Decimator Control Register 1 DEC_CR1 is used to configure the decimator prior to using it Bit 7 ECNT The ECNT bit is a mode bit that controls the operation of the ...

Page 359: ...he PSoC device and possibly stall the bus 2 Since receive and transmitted data are not buffered there is no support for automatic receive acknowledge The M8C microcontroller must intervene at the boundary of each byte and either send a byte or ACK received bytes The I2C block is designed to support a set of primitive oper ations and detect a set of status conditions specific to the I2C protocol Th...

Page 360: ...ions on the bus Figure 28 2 is a graphical representation of a typical data transfer from the slave perspective Figure 28 2 Slave Operation 1 7 8 9 1 7 8 9 START 7 Bit Address R W ACK 8 Bit Data ACK NACK STOP 1 7 8 1 7 8 9 START 7 Bit Address R W ACK 8 Bit Data ACK NACK STOP SHIFTER M8C reads the received byte from the I2C_DR register and checks for Own Address and R W 1 7 8 8 Bit Data STOP SHIFTE...

Page 361: ...ting in Slave mode In this case the data register has the master s address data 2 If another master starts a transmission at the same time as this unit arbitration occurs If this unit loses the arbi tration the LostArb status bit is set In this case the block releases the bus and switches to slave operation When the Start Address interrupt occurs the data regis ter has the winning master s address...

Page 362: ...esistive zero Drive mode before reaching the High Z Drive mode After a POR event P1 0 drives out a one then goes to the resistive zero state for some time and finally reaches the High Z Drive mode state After POR P1 1 goes into a resistive zero state for a while before going to the High Z Drive mode Another issue with selecting the alternate I2C pins set is that these pins are also the crystal pin...

Page 363: ...n operating as a slave the block is clocked from an external master Therefore the block works at any frequency up to the maximum defined by the currently selected clock rate The internal clock is only used in Slave mode to ensure that there is adequate set up time from data output to the next clock on the release of a slave stall When the Enable Slave and Enable Master bits are both 0 the block is...

Page 364: ... an ACK Any other timing for a start condition causes the Bus Error bit to be set A stop is only valid if the block is idle or a slave receiver is ready to receive the first bit of a new byte after an ACK Any other timing for a stop condition causes the Bus Error bit to be set Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0 D7h I2C_SCR Bus Error Lost Arb Stop Status ACK Addre...

Page 365: ...reads the received address from the data register and compares it with its own address If the address does not match the firmware writes a NACK indication to this register No further interrupts occur until the next address is received If the address does match firmware must ACK the received byte then Byte Complete interrupts are generated on sub sequent bytes of the transfer This bit is also sets ...

Page 366: ...Address bytes must be writ ten in I2C_DR before the Start or Restart bit is set in the I2C_MSCR register which causes the start or restart to generate and the address to shift out Master or Slave Transmitter Data bytes must be writ ten to the I2C_DR register before the transmit bit is set in the I2C_SCR register which causes the transfer to con tinue For additional information refer to the I2C_DR ...

Page 367: ...lave mode is not enabled A start and address byte interrupt is generated The Start Gen bit is cleared and the Lost Arb bit is set The hardware waits for command input stalling the bus if necessary In this case the mas ter clears the I2C_SCR register to release the bus and allow the transfer to continue and the block idles Other cases where the Start bit is used to generate a Start condition are as...

Page 368: ...the two divider taps is selected that clock is resynchronized to SYSCLK The resulting clock is routed to all of the synchronous ele ments in the design Figure 28 4 I2C Input Clocking 28 4 2 Basic Input Output Timing Figure 28 5 illustrates basic input output timing that is valid for both 16 times sampling and 32 times sampling For 16 times sampling N 4 and for 32 times sampling N 12 N is derived f...

Page 369: ... Figure 28 6 Byte Complete Address LRB Timing Figure 28 7 shows the timing for Stop Status This bit is set and the interrupt occurs two clocks after the synchronized and filtered SDA line transitions to a 1 when the SCL line is high Figure 28 7 Stop Status and Interrupt Timing Figure 28 8 illustrates the timing for bus error interrupts Bus Error status and Interrupt occurs one cycle after the inte...

Page 370: ...ernal start is detected the start sequence is aborted and the block returns to an IDLE state However on the next stop detection the block automatically initiates a new Start sequence Figure 28 9 Basic Master Start Timing Figure 28 10 Start Timing with a Pending Start CMD START SDA CLOCK SCL START DETECT I O WRITE 6 14 Clocks 8 16 Clocks 5 Clocks 8 16 Clocks to next SCL high SCL SDA CLOCK BUS BUSY ...

Page 371: ...art Timing 28 4 6 Master Stop Timing Figure 28 13 shows basic Master Stop timing In order to generate a stop the SDA line is first pulled low in accordance with the basic SDA output timing Then after the full low of SCL is completed and the SCL line is pulled high the SDA line remains low for a full 1 half bit time before it is pulled high to signal the stop Figure 28 13 Master Stop Timing SCL SDA...

Page 372: ...28 15 shows a Lost Arbitration sequence When contention is detected at the input SDA_IN sampling point the SDA output is immediately released to an IDLE state However the master continues clocking until the Byte Complete interrupt which is processed in the usual way Any write to the I2C_SCR register results in the master reverting to an IDLE state one clock after the next positive edge of the SCL_...

Page 373: ...or input synchronization of three clocks giving a net period of 8 16 clocks for both high and low time This results in an overall clocking rate of 16 32 clocks per bit In multi master environments when the hardware outputs a 1 on the SCL output if any other master is still asserting a 0 the clock counter holds until the SCL input line matches the 1 on the SCL output line When matched the remainder...

Page 374: ...310 Document 001 20559 Rev D I2C ...

Page 375: ...bandgap voltage generator and a buffer with sample and hold The bandgap voltage generator is a typical VBE K VT design The buffer circuit provides gain to the 1 20V bandgap volt age to produce a 1 30V reference A simplified schematic is illustrated in Figure 29 1 The connection between ampli fier and capacitor is made through a CMOS switch allowing the reference voltage to be used by the system wh...

Page 376: ...filter to AGND R is an internal 8 1K resistor and C is external to the PSoC device on P2 4 Bits 5 and 4 TC 1 0 These bits are for setting the tem perature coefficient inside the bandgap voltage generator 10b is the design center for 0 TC It is strongly recommended that the user not alter the value of these bits Bits 3 to 0 V 3 0 These bits are for setting the gain in the reference buffer Sixteen s...

Page 377: ...high reset is driven into the PSoC device on parts that contain an XRES pin Watchdog Reset WDR This optional reset occurs when the watchdog timer expires before being cleared by user firmware Watchdog reset defaults to off The occurrence of a reset is recorded in the Status and Con trol registers CPU_SCR0 for POR XRES and WDR or in the System Status and Control Register 1 Firmware can interrogate ...

Page 378: ...as been previ ously written to It is read only When this bit is a 1 this indi cates that the CPU_SCR1 register has been written to and is now locked When this bit is a 0 the register has not been written to since the last reset event Note that this bit cannot be used by the CY8C27x43 for silicon revision A and by the CY8C24533 CY8C23533 CY8C23433 CY8C24633 CY8C24x23 and CY8C22x13 PSoC devices Bit ...

Page 379: ...eep bit is used to enter Low Power Sleep mode when set To wake up the system this register bit is cleared asynchronously by any enabled interrupt There are two special features of this register bit that ensures proper sleep operation First the write to set the register bit is blocked if an interrupt is about to be taken on that instruction boundary immediately after the write Sec ond there is a ha...

Page 380: ...OR does reset this register 30 4 2 Watchdog Timer Reset The user has the option to enable the Watchdog Timer Reset WDR by clearing the PORS bit in the CPU_SCR0 register Once the PORS bit is cleared the watchdog timer cannot be disabled The only exception to this is if a POR XRES event takes place which disables the WDR Note that a WDR does not clear the Watchdog timer See Watchdog Timer on page 40...

Page 381: ...ES IMO PD IMO not to scale CPU Reset PPOR with no IPOR Reset while PPOR is high and to the end of the next 32K cycle IMO off 1 cycle IMO on before the CPU reset is released Note that at the 5V level PPOR tends to be brief because the reset clears the POR range register VLT_CR back to the default 3V setting CLK32 PPOR Sleep Timer 0 1 2 Reset IPOR PPOR IMO PD IMO not to scale CPU Reset XRES Reset wh...

Page 382: ...set is de asserted Table 30 1 Details of Functionality for Various Resets Item IPOR Part of POR PPOR Part of POR XRES WDR Reset Length While POR 1 While PPOR 1 plus 30 60 s 1 2 clocks While XRES 1 30 s 1 clock Low Power IMO Off During Reset Yes Yes Yes No Low Power Wait Following Reset No No No No CLK32K Cycles from End of Reset to CPU Reset De assertsa a CPU reset is released after synchronizatio...

Page 383: ...7 31 1 Architectural Description The Power on Reset POR and Low Voltage Detect LVD circuits provide protection against low voltage conditions The POR function senses Vdd and holds the system in reset until the magnitude of Vdd supports operation to specifica tion The LVD function senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold Other outputs and status b...

Page 384: ... the Elec trical Specifications section of the PSoC device data sheet for voltage tolerances for each setting Bit 3 LVDTBEN This bit is AND ed with LVD to produce a throttle back signal that reduces CPU clock speed when low voltage conditions are detected When the throttle back sig nal is asserted the CPU speed bits in the OSC_CR0 regis ter are reset forcing the CPU speed to 3 MHz or EXTCLK 8 Bits...

Page 385: ...r number identifying the memory location RAM ROM or register where a unit of information is stored algorithm A procedure for solving a mathematical problem in a finite number of steps that frequently involve repetition of an operation ambient temperature The temperature of the air in a designated area particularly the area surrounding the PSoC device analog See analog signals analog blocks The bas...

Page 386: ...of any clock sig nal attenuation The decrease in intensity of a signal as a result of absorption of energy and of scattering out of the path to the detector but not including the reduction due to geometric spreading Attenuation is usually expressed in dB B bandgap reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coeff...

Page 387: ...r OR and for AND for example A B since in some ways those opera tions are analogous to addition and multiplication in other algebraic structures and represent NOT by a line drawn above the expression being negated for example A A_ A break before make The elements involved go through a disconnected state entering break before the new con nected state make broadcast net A signal that is routed throu...

Page 388: ...age such as C into machine language configuration In a computer system an arrangement of functional units according to their nature number and chief characteristics Configuration pertains to hardware software firmware and documenta tion The configuration affects system performance configuration space In PSoC devices the register space accessed when the XIO bit in the CPU_F register is set to 1 cro...

Page 389: ...itter CRC generator pseudo random number generator or SPI digital logic A methodology for dealing with expressions containing two state variables that describe the behavior of a circuit or system digital to analog DAC A device that changes a digital signal to an analog signal of corresponding magnitude The ana log to digital ADC converter performs the reverse operation direct access The capability...

Page 390: ...e corresponding signal frequency The number of cycles or events per unit of time for a periodic function G gain The ratio of output current voltage or power to input current voltage or power respectively Gain is usually expressed in dB gate 1 A device having one output channel and one or more input channels such that the output channel state is completely determined by the input channel states exc...

Page 391: ...th resistors The bus operates at 100 kbits second in stan dard mode and 400 kbits second in fast mode I2C is a trademark of the Philips Semiconduc tors ICE The in circuit emulator that allows users to test the project in a hardware environment while viewing the debugging device activity in a software environment PSoC Designer idle state A condition that exists whenever user messages are not being ...

Page 392: ... a binary number that represents the least significant value typically the right hand bit The bit versus byte distinction is made by using a lower case b for bit in LSb least significant byte LSB The byte in a multi byte word that represents the least significant values typically the right hand byte The byte versus bit distinction is made by using an upper case B for byte in LSB Linear Feedback Sh...

Page 393: ...ization of a controller with a minimal quantity of chips thus achieving maximal possible miniaturization This in turn reduces the volume and the cost of the controller The microcontroller is normally not used for general purpose computation as is a microprocessor mnemonic A tool intended to assist the memory Mnemonics rely on not only repetition to remember facts but also on creating associations ...

Page 394: ...ne parameter Characteristics for a given block that have either been characterized or may be defined by the designer parameter block A location in memory where parameters for the SSC instruction are placed prior to execution parity A technique for testing transmitting data Typically a binary digit is added to the data to make the sum of all the digits of the binary data either always even even par...

Page 395: ...address of the next instruction to be executed protocol A set of rules Particularly the rules that govern networked communications PSoC Cypress Semiconductor s Programmable System on Chip PSoC PSoC is a registered trade mark and Programmable System on Chip is a trademark of Cypress PSoC blocks See analog blocks and digital blocks PSoC Designer The software for Cypress Programmable System on Chip t...

Page 396: ...s of a logic diagram for a computer seed value An initial value loaded into a linear feedback shift register or random number generator serial 1 Pertaining to a process in which all events occur one after the other 2 Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel set To force a bit register to a value of logic 1 settling time ...

Page 397: ...e that is used to boot the device calibrate circuitry and perform Flash operations The functions of the SROM may be accessed in normal user code operating from Flash stack A stack is a data structure that works on the principle of Last In First Out LIFO This means that the last item put on the stack is the first item that can be taken off stack pointer A stack may be represented in a computer s in...

Page 398: ...e function does not drive any value in the Z state and in many respects may be considered to be disconnected from the rest of the circuit allowing another output to drive the same net U UART A UART or universal asynchronous receiver transmitter translates between parallel bits of data and serial bits user The person using the PSoC device and reading this manual user modules Pre built pre tested ha...

Page 399: ... Glossary W watchdog timer A timer that must be serviced periodically If it is not serviced the CPU resets after a specified period of time waveform The representation of a signal as a plot of amplitude versus time X XOR See Boolean Algebra ...

Page 400: ...336 Document 001 20559 Rev D Section G Glossary ...

Page 401: ...er 159 address spaces CPU core 35 addressing modes M8C 39 ADI See array digital interconnect AGNDBYP bit 222 376 in BDG_TR register 222 AINT bits 130 Align Enable bit 135 Align Source bits 135 ALT_CR0 register 202 295 AMD_CR0 register 200 295 AMD_CR1 register 201 295 AMOD0 bits in AMD_CR0 register 200 AMOD1 bits in AMD_CR1 register 201 amplifiers instruction 315 AMux bits 144 AMux connections 301 ...

Page 402: ...ter 148 324 ASCxxCR2 register 149 324 ASCxxCR3 register 150 325 ASDxxCR0 register 143 326 ASDxxCR1 register 144 327 ASDxxCR2 register 145 327 ASDxxCR3 register 146 328 ASign bit in ASCxxCR0 register 147 in ASDxxCR0 register 143 ASY_CR register 131 291 asynchronous receiver function 249 asynchronous transmitter function 249 AutoZero bit in ASCxxCR2 register 149 in ASDxxCR2 register 145 AUX IO Selec...

Page 403: ...unctionality 244 register definitions 253 timing 263 CPhase bit 142 CPU core 35 address spaces 35 addressing modes 39 instruction formats 38 instruction set summary 36 37 internal M8C registers 35 overview 35 register definitions 44 CPU Sleep bit 92 215 CPU speed settings 88 100 CPU_F register 44 59 67 184 CPU_SCR0 register 99 186 379 CPU_SCR1 register 51 80 87 98 185 378 CRCPRS for digital blocks...

Page 404: ... protocol function 247 SPI slave function 248 timer function 243 timing diagrams 262 digital blocks timing diagrams counter timing 263 CRCPRS timing 266 dead band timing 264 receiver timing 275 SPI mode timing 266 SPIM timing 267 SPIS timing 270 timer timing 262 transmitter timing 273 digital clocks 339 32 KHz crystal oscillator 341 architecture 339 device distinctions 342 external clock 341 inter...

Page 405: ...75 register definitions 72 GIE bit 44 59 67 184 GIENOUTx bits in GDI_E_IN register 209 GIES bit 186 GIONOUTx bits in GDI_O_IN register 208 global digital interconnect 229 28 to 32 pin global interconnect 230 architecture 229 register definitions 231 global IO in GPIO 70 Global Select bits 115 global select bits 73 GOEUTINx bits in GDI_E_OU register 211 GOExEN bit 156 157 GOOUTINx bits in GDI_O_OU ...

Page 406: ...lication description 63 architecture 61 interrupt table 63 latency and priority 62 posted versus pending interrupts 62 register definitions 64 Interrupt Enables bits 114 interrupt enables bits 72 interrupt mask registers in digital blocks INT_MSK1 register 257 interrupt table for PSoC devices 63 interrupts in RAM paging 56 IRAMDIS bit 51 80 87 185 IRESS bit 51 80 87 185 ISx bits 153 L look up tabl...

Page 407: ...RTxDM0 register 74 187 PRTxDM1 register 74 188 PRTxDM2 register 74 116 PRTxDR register 72 113 PRTxGS register 73 115 PRTxIC0 register 75 189 PRTxIC1 register 75 190 PRTxIE register 72 114 PSelect bit 158 PSoC core architecture 31 overview 18 PSoC device characteristics 20 distinctions 20 PSSDC bit in ECO_TR register 223 PUMP bit 219 PWR bit in ABF_CR0 register 307 PWR bits in ABF_CR0 register 78 1...

Page 408: ...ister 168 SAR8 ADC PSoC Block 329 architecture 329 features 329 register definitions 330 SARADC_CR0 register 134 330 SARADC_CR1 register 135 331 SARADC_CR2 register 206 334 SARADC_DL register 133 330 SARADC_LCR register 207 334 SARADC_TRCH register 205 333 SARADC_TRCL register 204 333 SARADC_TRS register 203 332 SARCNT bits 131 SARCOL bits 131 SARSIGN bit 131 SC type C control registers 323 SC typ...

Page 409: ...wer on reset 380 register definitions 378 timing diagrams 380 watchdog timer reset 380 system resources architecture 335 characteristics 335 overview 18 335 register summary 336 T TableRead function in SROM 49 TC bits in BDG_TR register 222 TC Pulse Width bit 120 temperature sensing in analog 303 Test Enable bit in SARADC_CR2 register 206 TestMux bits 142 timer for digital blocks functionality 243...

Page 410: ...410 Document 001 20559 Rev D Index W watchdog timer reset 380 WDRS bit 186 WDSL_Clear bits 171 WriteBlock function in SROM 48 X XIO bit 44 59 184 Z Zero bit 44 59 184 ...

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