Cypress PSoC CY8C23533, Technical Reference Manual

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222 Document # 001-20559 Rev. *D
Analog Interface
The ICLKS bits, which are split between the DEC_CR0 and
DEC_CR1 registers, are used to select a source for the
incremental gating signal. The four IGEN bits are used to
independently enable the gating function on a column-by-
column basis.
18.1.5 Analog Modulator Interface (Mod
Bits)
The Analog Modulator Interface provides a selection of sig-
nals that are routed to any of the four analog array modula-
tion control signals. There is one modulation control signal
for each Type C Analog Switched Capacitor block in every
analog column. There are eight selections, which include
the analog comparator bus outputs, two global outputs, and
a digital block broadcast bus. The selections for all columns
are identical and are contained in the AMD_CR0 and
AMD_CR1 registers. The Mod bit is XOR’ed with the
switched capacitor block
sign bit (ASign in ASCxxCR0) to
provide dynamic control of that bit.
18.1.6 Analog Synchronization Interface
(Stalling)
For high precision analog operation, it is necessary to pre-
cisely time when updated register values are available to the
analog PSOC blocks. The optimum time to update values in
Switched Capacitor registers is at the beginning of the PHI1
active period. Depending on the relationship between the
CPU CLK and the analog column clock, the CPU IO write
cycle can occur at any 24 MHz master clock boundary in the
PHI1 or PHI2 cycle. Register values may be written at arbi-
trary times; however, glitches may be apparent at analog
outputs. This is because the capacitor value is changing
when the circuit is designed to be settling.
The SYNCEN bit in the Analog Synchronization Control reg-
ister (ASY_CR) is designed to address this problem. When
the SYNCEN bit is set, an IO write instruction to any
Switched Capacitor register is blocked at the interface and
the CPU stalls. On the subsequent rising edge of PHI1, the
CPU stall is released, allowing the IO write to be performed
at the destination analog register. This mode synchronizes
the IO write action to perform at the optimum point in the
analog cycle, at the expense of CPU
bandwidth .
Figure 18-4 shows the timing for this operation.
Figure 18-4. Synchronized Write to a DAC Register
As an alternative to stalling, the source for the analog col-
umn interrupts is set as the falling edge of the PHI2 clock.
This configuration synchronizes the CPU to perform the IO
write after the PHI2 phase is completed, which is equivalent
to the start of PHI1.
18.2 PSoC Device Distinctions
The DEC_CR1 register’s bit 7 (ECNT) is only available in
PSoC devices with a type 1 decimator and is reserved in
PSoC devices with a type 2 decimator.
18.3 Application Description
18.3.1 SAR Hardware Acceleration
The Successive Approximation Register (SAR) algorithm is
a binary search on the Digital-to-Analog Converter (DAC)
code that best matches the input voltage being measured.
The first step is to take an initial guess at mid-scale, which
effectively splits the range by half. The DAC output value is
then compared to the input voltage. If the guess is too low, a
result bit is set for that binary position and the next guess is
set at mid-scale of the remaining upper range. If the guess
is too high, a result bit is cleared and the next guess is set at
mid-scale of the remaining lower range. This process is
repeated until all bits are tested. The resulting DAC code is
the value that produces an output voltage closest to the
input voltage. This code should be within one LSb of the
input voltage.
The successive approximation analog-to-digital algorithm
requires the following building blocks: a DAC, a comparator,
and a method or apparatus to sequence successive writes
to the DAC based on the comparator output. The SAR hard-
ware accelerator represents a trade off between a fully auto-
matic hardware sequencing approach and a pure firmware
approach.
CPUCLK
nerated)
CPUCLK
To CPU)
IOW
STALL
PHI
CLK24
AIOW
Stall is released here.
AIOW
completes here.