Cypress PSoC CY8C23533, Technical Reference Manual

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282 Document # 001-20559 Rev. *D
Digital Clocks
25.3.6 OSC_CR0 Register
The Oscillator Control Register 0 (OSC_CR0) is used to
configure various features of internal clock sources and
clock nets.
Bit 7: 32k Select. By default, the 32 kHz clock source is
the Internal Low Speed Oscillator (ILO). Optionally, the
32.768 kHz External Crystal Oscillator (ECO) may be
selected.
Bit 6: PLL Mode. This bit is the only bit that directly influ-
ences the PLL. When set, it enables the PLL. The EXTCLK
bit should be set low during PLL operation.
Bit 5: No Buzz. Normally, when the Sleep bit is set in the
CPU_SCR register, all PSoC device systems are powered
down, including the bandgap reference. However, to facili-
tate the detection of POR and LVD events at a rate higher
than the sleep interval, the bandgap circuit is powered up
periodically (for about 60

s) at the Sleep System Duty
Cycle (set in ECO_TR), which is independent of the sleep
interval and typically higher. When the No Buzz bit is set, the
Sleep System Duty Cycle value is overridden and the band-
gap circuit is forced to be on during sleep. This results in
faster response to an LVD or POR event (continuous detec-
tion as opposed to periodic), at the expense of slightly
higher average sleep current.
Bits 4 and 3: Sleep[1:0]. The available sleep interval
selections are shown in Table 25-4 . Remember that when
the ILO is the selected 32 kHz clock source, sleep intervals
are approximate.
Bits 2 to 0: CPU Speed[2:0]. The PSoC M8C operates
over a range of CPU clock speeds ( Table 25-5 ), allowing the
M8C’s performance and power requirements to be tailored
to the application.
The reset value for the CPU speed bits is zero. Therefore,
the default CPU speed is one-eighth of the clock source.
The internal main oscillator is the default clock source for
the CPU speed circuit; therefore, the default CPU speed is 3
MHz. See
“External Clock” on page 277 for more informa-
tion on the supported frequencies for externally supplied
clocks.
The CPU frequency is changed with a write to the
OSC_CR0 register. There are eight frequencies generated
from a power-of-two divide circuit, which are selected by a
3-bit code. At any given time, the CPU 8-to-1 clock mux is
selecting one of the available frequencies, which is resyn-
chronized to the 24 MHz master clock at the output.
Regardless of the CPU speed bit’s setting, if the actual CPU
speed is greater than 12 MHz, the 24 MHz operating
requirements apply. An example of this scenario is a device
that is configured to use an external clock, which is supply-
ing a frequency of 20 MHz. If the CPU speed register’s
value is 0x03, the CPU clock is 20 MHz. Therefore, the sup-
ply voltage requirements for the device are the same as if
the part was operating at 24 MHz off of the internal main
oscillator. The operating voltage requirements are not
relaxed until the CPU speed is at 12.0 MHz or less.
Some devices support the slow IMO option, as discussed in
the IMO chapter in the
“Architectural Description” on
page 15 . This offers an option to lower both system and
CPU clock speed in order to save power.
An automatic protection mechanism is available for systems
that need to run at peak CPU clock speed but cannot guar-
antee a high enough supply voltage for that clock speed.
See the LVDTBEN bit in the
“VLT_CR Register” on
page 320 for more information.
For additional information, refer to the OSC_CR0 register on
page 151 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,E0h OSC_CR
0 32k Select PLL Mode No Buzz Sleep[1:0] CPU Speed[2:0] RW : 00
Table 25-4. Sleep Interval Selections
Sleep Interval
OSC_CR[4:3]
Sleep Timer
Clocks
Sleep Period
(nominal)
Watchdog
Period
(nominal)
00b (default) 64 1.95 ms 6 ms
01b 512 15.6 ms 47 ms
10b 4096 125 ms 375 ms
11b 32,768 1 sec 3 sec
Table 25-5. OSC_CR0[2:0] Bits: CPU Speed
Bits
6 MHz Internal
Main Oscillator *
24 MHz Internal
Main Oscillator
External Clock
000b 750 kHz 3 MHz EXTCLK/ 8
001b 1.5 MHz 6 MHz EXTCLK/ 4
010b 3 MHz 12 MHz EXTCLK/ 2
011b 6 MHz 24 MHz EXTCLK/ 1
100b 375 kHz 1.5 MHz EXTCLK/ 16
101b 187.5 kHz 750 kHz EXTCLK/ 32
110b 93.7 kHz 187.5 kHz EXTCLK/ 128
111b 23.4 kHz 93.7 kHz EXTCLK/ 256
* For PSoC devices that support the slow IMO option, see the
“Architec-
tural Description” on page 15
.