Cypress PSoC CY8C23533, Technical Reference Manual

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230 Document # 001-20559 Rev. *D
Analog Interface
18.4.6 CLK_CR0 Register
The Analog Clock Source Control Register 0 (CLK_CR0) is
used to select the clock source for an individual analog col-
umn.
An analog column clock generator is provided for each col-
umn. The bits in this register select the source for each col-
umn clock generator. Regardless of the source selected, the
input clock is divided by four to generate the PHI1/PHI2 non-
overlapping clocks for the column.
There are four selections for each clock: VC1, VC2, ACLK0,
and ACLK1. VC1 and VC2 are the programmable global
system clocks. ACLK0 and ACLK1 sources are each
selected from one up to eight digital block outputs (function-
ing as clock generators).
Bits 3 and 2: AColumn1[1:0]. These bits select the source
for analog column 1.
Bits 1 and 0: AColumn0[1:0]. These bits select the source
for analog column 0.
For additional information, refer to the CLK_CR0 register on
page 133 .
18.4.7 CLK_CR1 Register
The Analog Clock Source Control Register 1 (CLK_CR1) is
used to select the clock source for an individual analog col-
umn.
Bit 6: SHDIS. The SHDIS bit functions as follows. During
normal operation of an SC block, for the amplifier of a col-
umn enabled to drive the output bus, the connection is only
made for the last half of PHI2. (During PHI1 and for the first
half of PHI2, the output bus floats at the last voltage to which
it was driven.) This forms a sample and hold operation using
the output bus and its associated
capacitance . This design
prevents the output bus from being perturbed by the inter-
mediate states of the SC operation (often a reset state for
PHI1 and settling to the valid state during PHI2).
The following are the exceptions: 1) If the ClockPhase bit in
ASCxx_CR0 (for the SC block in question) is set to ‘1’, then
the output is enabled if the analog bus output is enabled
during both PHI1 and PHI2. 2) If the SHDIS signal is set in
bit 6 of the Analog Clock Source Control register, then sam-
ple and hold operation is disabled for all columns and all
enabled outputs of SC blocks are connected to their respec-
tive output buses, for the entire period of their respective
PHI2s.
Bits 5 to 0: ACLKx[2:0]. There are two 3-bit fields in this
register that can select up to one of eight digital blocks
(depending on the PSoC device resources), to function as
the clock source for ACLK0 and ACLK1. ACLK0 and ACLK1
are alternative clock inputs to the analog column clock gen-
erators (see the CLK_CR0 register above).
For additional information, refer to the CLK_CR1 register on
page 134 .
Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,60h
CLK_CR0 AColumn1[1:0] AColumn0[1:0] RW : 0
Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
1,61h CLK_CR1 SHDIS ACLK1[2:0] ACLK0[2:0] RW : 00