Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 211
Digital Blocks
17.3.9 Receiver Timing
Enable/Disable Operation. As soon as the block is config-
ured for receiver and before enabling, the primary output is
connected to the data input (RXD). This output continues to
follow the input, regardless of enable state. The auxiliary
output idles to '1', which is the idle state of the associated
SPI mode 3 clock.
When the receiver is enabled, the internal clock generator is
held in reset until a START bit is detected on the input. The
block must be enabled with a set up time to the first START
bit input.
When the block is disabled, the clock is immediately gated
low. All internal states are reset (including CR0 status) to
their configuration-specific reset state, except for DR0, DR1,
and DR2 which are unaffected.
Receive Operation. A clock, which must be eight times the
desired baud rate, is selected as the CLK input. This clock is
an input to the RX block clock divider. When the receiver is
idle, the clock divider is held in reset. As shown in
Figure 17-27 , reception is initiated when a START bit (logic
0) is detected on the RXD input.
When this occurs, the reset is negated to the clock divider
and the 3-bit counter starts an up-count. The block clock is
derived from the MSb of this counter (corresponding to a
count of four), which serves to sample each incoming bit at
the nominal center point. This clock also sequences the
state machine at the specified bit rate.
The sampled data is registered into an input flip-flop. This
flip-flop feeds the DR0 shift register. Only data bits are
shifted into the shift register.
At the STOP sample point, the block is immediately (within
one cycle of the 24 MHz system clock) set back into an idle
state. In this way, the clock generation circuit can immedi-
ately enable the search for the next START bit, thereby
resynchronizing the bit clock with the incoming bit rate on
every new data byte reception. The RX Reg Full status bit,
as well as error status, is also set at the STOP sample point.
To facilitate connection to other digital blocks, the RXD input
is passed directly to the RXDOUT (primary) output. The
SCLK (auxiliary) output has an SPI mode 3 clock associated
with the data bits (for mode 3 timing see
Figure 17-27 ). Dur-
ing the mark (idle) and framing bits, the SCLK output is high.
Figure 17-27. Receiver Operation
Clock Generation and Start Detection. The input clock
selection is a free running, eight times over-sampling clock.
This clock is used by the clock divider circuit to generate the
block clock at the bit rate. As shown in
Figure 17-28 , the
clock block is derived from the MSb of a 3-bit counter, giving
a sample point as near to the center of the bit time as possi-
ble. This block clock is used to clock all internal circuits.
Since the RXD bit rate is asynchronous to the block bit
clock, these clocks must be continually re-aligned. This is
accomplished with the START bit detection.
When in IDLE state, the clock divider is held in reset. On
START (when the input RXD transitions are detected as a
logic 0), the reset is negated and the divider is enabled to
count at the eight times rate. If the RXD input is still logic 0
after three samples of the input clock, the status RXACTIVE
is asserted, which initiates a reception. If this sample of the
RXD line is a logic 1, the input '0' transition is assumed to be
a false start and the receiver remains in the idle state.
CCLK
RXD
IDLE
START
BIT0 STATE BIT6 BIT7
Start bit is
detected;
clock divider
is enabled.
Input is sampled at the
center of the bit time.
SCLK (F2)
PAR START BIT0
D0 D1 D6 D7 PAR D0
Clock divider is
resynchronized from IDLE
on detection of the next
START bit.
D0 D1 D6 D7 PAR D0
RXDOUT (F1)
Serial data is
passed through to
the primary output.
Mode 3 type clock on auxiliary
output for data only.
RX buffer is loaded with the
received byte and status is set
on STOP bit detection edge.
IDLE
STOP
At STOP edge, FSM is
reset to IDLE to search
for next START after one
24 MHz clock (42 ns).
RX REG FULL