Document # 001-20559 Rev. *D
219
18.
Analog Interface
This chapter explains the Analog Interface and its associated registers. The analog system interface is a collection of system
level interfaces to the analog array and analog reference block. For a complete table of the analog interface registers, refer to
the
“Summary Table of the Analog Registers” on page 217
. For a quick reference of all PSoC registers in address order, refer
Register Details chapter on page 47
.
18.1
Architectural Description
displays the top-level diagram of the PSoC device’s analog interface system. This diagram displays Analog Col-
umn 1 for the CY8C24533, CY8C23533, CY8C23433CY8C24633 devices. Analog Column 0 for this device includes one CT
(Continuous Time) block and the SAR8 ADC block, rather than the two standard SC (Switched Capacitor) blocks.
Figure 18-1. Analog Comparator Bus Slice
Latch
CMP
CBUS
Driver
Transparent, PHI1 or PHI2
Latch
PHI2
BYPASS
(CLDIS, CMP_CR1[7:4])
To Col (i-1)
LUT
From Col (i+1)
IGEN[1:0]
Incremental Gate, One per Column
(From Digital Blocks)
Destinations
1) Comparator
Register
2) Data Inputs
for Digital
Blocks
3) Input to
Decimator
Column
Interrupt
PHI2
One Analog Column
Output to SAR Accelerator Input Mux
Analog Comparator Bus Slice
Continuous Time Block
Latch
CMP
CBUS
Driver
PHI1 or PHI2
Switched Capacitor Block
Latch
CMP
CBUS
Driver
PHI1 or PHI2
Switched Capacitor Block
Data Output
From DCB03
Data Output
From DBB00
Data Output
From DCB02
Data Output
From DBB01
A
B
(DEC_CR0[5:4])
(ALT_CR0[7:0])
AINT (CMP_CR0[1:0])
Summary of Contents for PSoC CY8C23533
Page 4: ...Contents Overview 4 Document 001 20559 Rev D Section G Glossary 385 Index 401 ...
Page 16: ...Contents Overview 16 Document 001 20559 Rev D ...
Page 24: ...24 Document 001 20559 Rev D Section A Overview ...
Page 30: ...30 Document 001 20559 Rev D Pin Information ...
Page 54: ...54 Document 001 20559 Rev D Supervisory ROM SROM ...
Page 60: ...60 Document 001 20559 Rev D RAM Paging ...
Page 68: ...68 Document 001 20559 Rev D Interrupt Controller ...
Page 76: ...12 Document 001 20559 Rev D General Purpose IO GPIO ...
Page 82: ...18 Document 001 20559 Rev D Internal Main Oscillator IMO ...
Page 84: ...20 Document 001 20559 Rev D Internal Low Speed Oscillator ILO ...
Page 90: ...26 Document 001 20559 Rev D External Crystal Oscillator ECO ...
Page 94: ...30 Document 001 20559 Rev D Phase Locked Loop PLL ...
Page 106: ...42 Document 001 20559 Rev D Sleep and Watchdog ...
Page 228: ...164 Document 001 20559 Rev D Section D Digital System ...
Page 234: ...170 Document 001 20559 Rev D Array Digital Interconnect ADI ...
Page 278: ...214 Document 001 20559 Rev D Digital Blocks ...
Page 296: ...232 Document 001 20559 Rev D Analog Interface ...
Page 304: ...240 Document 001 20559 Rev D Analog Array ...
Page 308: ...244 Document 001 20559 Rev D Analog Input Configuration ...
Page 312: ...248 Document 001 20559 Rev D Analog Reference ...
Page 338: ...274 Document 001 20559 Rev D Section F System Resources ...
Page 354: ...290 Document 001 20559 Rev D Multiply Accumulate MAC ...
Page 374: ...310 Document 001 20559 Rev D I2C ...
Page 400: ...336 Document 001 20559 Rev D Section G Glossary ...