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Document # 001-20559 Rev. *D
217
Section E: Analog System
Analog Register Summary
The table below lists all the PSoC registers for the analog system in address order within their system resource configuration.
The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’. The
naming conventions for the SC and CT registers and their arrays of PSoC blocks are detailed in their respective table title
rows.
Analog PSoC arrays are 2 column or 1 column devices. The CY8C24533, CY8C23533, CY8C23433CY8C24633 are 2 col-
umn devices.
Summary Table of the Analog Registers
Add.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
ANALOG INTERFACE REGISTERS
(page
)
0,64h
COMP[1:0]]
AINT[1:0]
# : 00
0,65h
SARCNT[2:0]
SARSIGN
SARCOL[1]
SYNCEN
RW : 00
0,66h
CLDIS[1]
CLDIS[0]
RW : 00
0,E6h
IGEN[1:0]
ICLKS0
DCOL[1:0]
DCLKS0
RW : 00
0,E7h
ECNT
IDEC
ICLKS3
ICLKS2
ICLKS1
DCLKS3
DCLKS2
DCLKS1
RW : 00
1,60h
AColumn1[1:0]
AColumn0[1:0]
RW : 00
1,61h
SHDIS
ACLK1[2:0]
ACLK0[2:0]
RW : 00
1,63h
AMOD0[2:0]
RW : 00
1,66h
AMOD1[2:0]
RW : 00
1,67h
LUT1[3:0]
LUT0[3:0]
RW : 00
ANALOG INPUT CONFIGURATION REGISTERS
(page
)
0,60h
ACI1[1:0]
ACI0[1:0]
RW : 00
1,62h
ACol1Mux
ABUF1EN
ABUF0EN
Bypass
PWR
RW : 00
ANALOG REFERENCE REGISTER
(page
)
0,63h
HBE
REF[2:0]
PWR[2:0]
RW : 00
CONTINUOUS TIME PSoC BLOCK REGISTERS
x,74h
LPCMPEN
CMOUT
INSAMP
EXGAIN
RW : 00
x,75h
RTapMux[3:0]
Gain
RTopMux
RBotMux[1:0]
RW : 00
x,76h
AnalogBus
CompBus
NMux[2:0]
PMux[2:0]
RW : 00
x,77h
CPhase
CLatch
CompCap
TMUXEN
TestMux[1:0]
PWR[1:0]
RW : 00
SWITCHED CAPACITOR PSoC BLOCK REGISTERS
(page
Switched Capacitor Block Registers, Type C
(page
)
x,94h
FCap
ClockPhase
ASign
ACap[4:0]
RW : 00
x,95h
ACMux[2:0]
BCap[4:0]
RW : 00
x,96h
AnalogBus
CompBus
AutoZero
CCap[4:0]
RW : 00
x,97h
ARefMux[1:0]
FSW1
FSW0
BMuxSC[1:0]
PWR[1:0]
RW : 00
Switched Capacitor Block Registers, Type D
(page
)
x,84h
FCap
ClockPhase
ASign
ACap[4:0]
RW : 00
x,85h
AMux[2:0]
BCap[4:0]
RW : 00
x,86h
AnalogBus
CompBus
AutoZero
CCap[4:0]
RW : 00
x,87h
ARefMux[1:0]
FSW1
FSW0
BSW
BMuxSD
PWR[1:0]
RW : 00
Summary of Contents for PSoC CY8C23533
Page 4: ...Contents Overview 4 Document 001 20559 Rev D Section G Glossary 385 Index 401 ...
Page 16: ...Contents Overview 16 Document 001 20559 Rev D ...
Page 24: ...24 Document 001 20559 Rev D Section A Overview ...
Page 30: ...30 Document 001 20559 Rev D Pin Information ...
Page 54: ...54 Document 001 20559 Rev D Supervisory ROM SROM ...
Page 60: ...60 Document 001 20559 Rev D RAM Paging ...
Page 68: ...68 Document 001 20559 Rev D Interrupt Controller ...
Page 76: ...12 Document 001 20559 Rev D General Purpose IO GPIO ...
Page 82: ...18 Document 001 20559 Rev D Internal Main Oscillator IMO ...
Page 84: ...20 Document 001 20559 Rev D Internal Low Speed Oscillator ILO ...
Page 90: ...26 Document 001 20559 Rev D External Crystal Oscillator ECO ...
Page 94: ...30 Document 001 20559 Rev D Phase Locked Loop PLL ...
Page 106: ...42 Document 001 20559 Rev D Sleep and Watchdog ...
Page 228: ...164 Document 001 20559 Rev D Section D Digital System ...
Page 234: ...170 Document 001 20559 Rev D Array Digital Interconnect ADI ...
Page 278: ...214 Document 001 20559 Rev D Digital Blocks ...
Page 296: ...232 Document 001 20559 Rev D Analog Interface ...
Page 304: ...240 Document 001 20559 Rev D Analog Array ...
Page 308: ...244 Document 001 20559 Rev D Analog Input Configuration ...
Page 312: ...248 Document 001 20559 Rev D Analog Reference ...
Page 338: ...274 Document 001 20559 Rev D Section F System Resources ...
Page 354: ...290 Document 001 20559 Rev D Multiply Accumulate MAC ...
Page 374: ...310 Document 001 20559 Rev D I2C ...
Page 400: ...336 Document 001 20559 Rev D Section G Glossary ...