Cypress PSoC CY8C23533, Technical Reference Manual

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66 Document # 001-20559 Rev. *D
0,64h
13.2.18 CMP_CR0
Analog Comparator Bus 0 Register
This register is used to poll the analog column comparator bits and select column interrupts.
Use the register tables above, in addition to the detailed register bit descriptions below, to determine which bits are reserved
for some smaller PSoC devices. Note that reserved bits are grayed table cells and are not described in the bit description sec-
tion below. Reserved bits should always be written with a value of ‘0’. For additional information, refer to the
“Register Defini-
tions” on page 227 in the Analog Interface chapter.
5 COMP[1] Comparator bus state for column 1.
This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the
CLDISx bits in the
CMP_CR1
register). If the comparator latch disable bits are set, then this bit is transpar-
ent to the comparator bus in the analog array.
4 COMP[0] Comparator bus state for column 0.
This bit is updated on the rising edge of PHI2, unless the comparator latch disable bits are set (refer to the
CLDISx bits in the
CMP_CR1
register). If the comparator latch disable bits are set, then this bit is transpar-
ent to the comparator bus in the analog array.
1 AINT[1] Controls the selection of the analog comparator interrupt for column 1.
0
The comparator data bit from the column is the input to the interrupt controller.
1 The falling edge of PHI2 for the column is the input to the interrupt controller.
0 AINT[0] Controls the selection of the analog comparator interrupt for column 0.
0
The comparator data bit from the column is the input to the interrupt controller.
1 The falling edge of PHI2 for the column is the input to the interrupt controller.
Individual Register Names and Addresses: 0,64h
CMP_CR0: 0,64h
7 6 5 4 3 2 1 0
Access : POR R : 0 RW : 0
Bit Name COMP[1:0] AINT[1:0]
Bits Name Description