Cypress PSoC CY8C23533, Technical Reference Manual

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Document # 001-20559 Rev. *D 227
Analog Interface
18.4 Register Definitions
The following registers are associated with the Analog Interface and are listed in address order. Each register description has
an associated register table showing the bit structure for that register. For a complete table of analog interface registers, refer
to the
“Summary Table of the Analog Registers” on page 217 .
The bits that are grayed out throughout this manual are reserved bits and are not detailed in the register descriptions that fol-
low. Reserved bits should always be written with a value of ‘0’.
18.4.1 CMP_CR0 Register
The Analog Comparator Bus Register 0 (CMP_CR0) is used
to poll the analog column comparator bits and select column
interrupts.
This register contains two fields: COMP and AINT. By
default, the interrupt is the comparator bit. A rising edge on a
comparator bit causes an interrupt to be registered. How-
ever, if a bit in this field is set, the interrupt input for that col-
umn is derived from the falling edge of PHI2 clock for that
column (that is, the falling edge of PHI2 leaves a rising inter-
rupt signal). Firmware can use this capability to synchronize
to the current column clock.
Bits 7 to 4: COMP[x]. These bits are the read only bits cor-
responding to the comparator bits in each analog column.
They are synchronized to the column clock, and thus may
be reliably polled by the CPU.
Bits 3 to 0: AINT[x]. These bits select the interrupt source
for each column, as the input to the interrupt controller.
For additional information, refer to the CMP_CR0 register on
page 66 .
18.4.2 ASY_CR Register
The Analog Synchronization Control Register (ASY_CR) is
used to control SAR operation, except for bit 0, SYNCEN.
SYNCEN is associated with analog register write stalling
and is described in
“Analog Synchronization Interface (Stall-
ing)” on page 222 .
The SAR hardware accelerator is a block of specialized
hardware designed to sequence the SAR algorithm for effi-
cient analog-to-digital conversion. A SAR ADC is imple-
mented conceptually with a DAC of the desired precision
and a comparator. This functionality is configured from one
or more PSoC blocks. For each conversion, the firmware ini-
tializes the ASY_CR register and sets the SIGN bit of the
DAC as the first guess in the algorithm. A sequence of OR
instructions (read, modify, write) to the ASxxxCR0 register is
then executed. Each of these OR instructions causes the
SAR hardware to read the current state of the comparator,
checking the validity of the previous guess. It either clears it
or leaves it set, accordingly. The next LSb in the DAC regis-
ter is also set as the next guess. Six OR instructions com-
plete the conversion of a 6-bit DAC.
The resulting DAC code, which matches the input voltage to
within one LSb, is then read back from the ASxxxCR0 regis-
ter.
Bits 6 to 4: SARCNT[2:0]. These bits are the SAR count
value and are used to initialize a three-bit counter to
sequence the six bits of the SAR algorithm. Typically, the
user initializes this register to ‘6’. When these bits are any
value other than ‘0’, a register read command to an SC
block is assumed to be part of a SAR sequence.
Assuming the comparator bus output is programmed for col-
umn 0, a typical firmware sequence is as follows.
mov reg[ASY_CR], 60h // SAR count value=6,
// Sign=0, Col=0
or reg[ASD11CR0], 0 // Check sign, set bit 4
or reg[ASD11CR0], 0 // Check bit 4, set bit 3
or reg[ASD11CR0], 0 // Check bit 3, set bit 2
or reg[ASD11CR0], 0 // Check bit 2, set bit 1
or reg[ASD11CR0], 0 // Check bit 1, set bit 0
or reg[ASD11CR0], 0 // Check bit 0
Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,64h
CMP_CR0 COMP[1:0] AINT[1:0] # : 00
#: Access is bit specific. Refer to the
Register Details chapter on page 47
.
Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,65h
ASY_CR SARCNT[2:0] SARSIGN SARCOL[1:0] SYNCEN
RW : 00