Artesyn MVME5100, Programmer'S Reference Manual, Page: 79 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
79
There are two exceptions that dynamically disable the PPC Timer. If the transaction is PCI
bound, then the burden of closing out a transaction is left to the PCI bus. Note that a
transaction to the PPC60x registers is considered to be PCI bound since the completion of
these types of accesses depends on the ability of the PCI bus to empty PCI bound write posted
data.
A second exception is the assertion of the XTOCLM_ signal. This is an open collector (wired OR),
bi-directional signal that is used by a bridge to indicate the burden of timing a transaction has
been passed on to another bus domain. The PHB asserts this signal whenever it has determined
that a transaction is being timed by its own PCI bus. Any other bridge devices listening to this
signal understand that the current pending cycle should not be subject to a time-out period.
During non-PCI bound cycles, the PPC Timer aborts the timing of the transaction any time it
detects XTOCLM_ has been asserted.
2.3.3 PCI Bus Interface
The PCI Interface of the PHB is designed to connect directly to a PCI Local Bus and supports
Master and Target transactions within Memory Space, I/O Space, and Configuration Space.
The section discusses the following topics:

PCI Address Mapping on page 79

PCI Slave on page 82

PCI FIFO on page 85

PCI Master on page 86

Generating PCI Cycles on page 89

PCI Arbiter on page 93
2.3.3.1 PCI Address Mapping
The PHB provides three resources to the PCI:

Configuration registers mapped into PCI Configuration space

PPC bus address space mapped into PCI Memory space

MPIC control registers mapped into either PCI I/O space or PCI Memory space
Configuration Registers