Artesyn MVME5100, Programmer'S Reference Manual, Page: 252 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
252
When rom b we is set, writes to Block B ROM/Flash are enabled. When rom b we is cleared, they
are disabled. Refer to
Table 3-27 for more details.
3.3.3.13 ROM Speed Attributes Registers
rom_a_spd0,1
rom_a_spd0,1 determine the access timing used for ROM/Flash Block A. The encoding of these
bits are shown in the following table.
The device access times shown in the table are conservative and allow time for buffers on
address, control, and data signals. For more accurate information see the section entitled
Timing Specifications for ROM/Flash Signals further on in this manual, along with the section
titled ROM/Flash Read Timing Diagram.
Writes that change these bits must be enveloped by a period of time in which no accesses to
ROM/Flash Block A, occur. A simple way to provide the envelope is to perform at least two
accesses to this or another of the SMC’s registers before and after the write.
Table 3-30 ROM Speed Attributes Registers
Address $FEF80060
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
0 0 rom a s
pd0
rom a s
pd1
0 0 rom b s
pd0
rom b s
pd0
Operation READ ZERO READ ZERO READ ZERO
R R R/W R/W R R R/W R/W
Reset X X X
X X 0 PL 0 PL X X 0 PL 0 PL
Table 3-31 ROM Speed Bit Encoding
rom_a/b_spd0,1 Approximate ROM Block A/B Device Access Time
%00 12 Clock Periods (120ns @ 100 MHz, 180ns @ 66.67 MHz)
%01 8 Clock Periods (80ns @ 100 MHz, 120ns @ 66.67 MHz)
%10 5 Clock Periods (50ns @ 100 MHz, 75ns @ 66.67 MHz)