Artesyn MVME5100, Programmer'S Reference Manual, Page: 303 / 318

MVME5100 VPD Reference Information
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
303
0A 1 L2C_OPERATIONMODE Operation Mode:
00 - Either Write-Through or Write-Back
(S/W Configurable)
01 - Either Write-Through or Write-Back
(H/W Configurable)
02 - Write-Through Only
03 - Write-Back Only
0B 1 L2C_ERROR_DETECT Error Detection Type:
00 - None
01 - Parity
02 - ECC
0C 1 L2C_SIZE L2 Cache Size (Should agree with the physical
organization above):
00 - 256K
01 - 512K
02 - 1M
03 - 2M
04 - 4M
0D 1 L2C_TYPE_BACKSIDE L2 Cache Type (Backside Configurations):
00 - Late Write Sync, 1nS Hold, Differential Clock,
Parity
01 - Pipelined Sync Burst, 0.5nS Hold, No
Differentia Clock, Parity
02 - Late Write Sync, 1nS Hold, Differential Clock,
No Parity
03 - Pipelined Sync Burst, 0.5nS Hold, No
Differential Clock, No Parity
0E 1 L2C_RATIO_BACKSIDE L2 Cache Core to Cache Ration (Backside
Configurations):
00 - Disabled
01 - 1:1 (1)
02 - 3:2 (1.5)
03 - 2:1 (2)
04 - 5:2 (2.5)
05 - 3:1 (3)
Table A-4 L2 Cache Configuration Data (continued)
Byte
Offset
Field
Size
(Bytes)
Field Mnemonic Field Description