Artesyn MVME5100, Programmer'S Reference Manual, Page: 259 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
259
The I2_DATAWR contains the transmit byte for I
2
C data transfers. If a value is written to
I2_DATAWR when the i2_start and i2_enbl bits in the I
2
C Control Register are set, a start
sequence is generated immediately followed by the transmission of the contents of the
I2_DATAWR to the responding slave device. The I2_DATAWR[24:30] is the device address, and
the I2_DATAWR[31] is the WR/RD bit (0=WRite, 1=ReaD). After a start sequence with
I2_DATAWR[31]=0, subsequent writes to the I
2
C Transmitter Data Register will cause the
contents of I2_DATAWR to be transmitted to the responding slave device. After a start
sequence with I2_DATAWR[31]=1, subsequent writes to the I
2
C Transmitter Data Register
(data=don’t care) will cause the responding slave device to transmit data to the I
2
C Receiver
Data Register. If a value is written to I2_DATAWR (data=don’t care) when the i2_stop and
i2_enbl bits in the I
2
C Control Register are set, a stop sequence is generated.
3.3.3.22 I
2
C Receiver Data Register
I2_DATARD
The I2_DATARD contains the receive byte for I
2
C data transfers. During I
2
C sequential read
operation, the current receive byte must be read before any new one can be borough in. A read
of this register will automatically clear the i2_datin bit in the I
2
C Status Register.
Table 3-40 I
2
C Receiver Data Register
Address $FEF800B0
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name I2_DATARD
Operation READ ZERO READ ZERO READ ZERO READ
Reset X X X 0 PL