Artesyn MVME5100, Programmer'S Reference Manual, Page: 33 / 318

Product Data and Memory Maps
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
33
The section discusses the following topics:
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Processors on page 33
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Processor Type Identification on page 33
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Processor PLL Configuration on page 34
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L2 Cache on page 34
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L2 Cache SRAM Size on page 34
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Cache Speed on page 34
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FLASH Memory on page 35
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ECC Memory on page 35
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P2 I/O Modes on page 36
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Serial Presence Detect (SPD) Definitions on page 36
1.3.1 Processors
The MVME5100 has the BGA foot print that supports the MPC750, MPC755 and MPC7410
processors. The maximum external processor bus speed is 100 MHz. Parity checking is
supported for the system address and data busses.
1.3.2 Processor Type Identification
The processor version can be determined by reading the Processor Version Register (PVR). The
PVR version number value for the MPC750 and MPC755 processors is 0x0008. The processor
revision level starts at 0x0100 and is updated for each silicon revision. For example, revision 1
of the MPC750 is 0x00080100. Revision 2 is 0x00080200, and so on. Incremental revisions,
such as 2.1, are identified as 0x00080201 and so on. For the MPC7410, the PVR version number
value is 0x000C, and the revision levels use the same nomenclature as the MPC750, e.g.,
0x0100 and so on.