Artesyn MVME5100, Programmer'S Reference Manual, Page: 158 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
158
2.5.2.5 MPIC I/O Base Address Register
The MPIC I/O Base Address Register (MIBAR) controls the mapping of the MPIC control
registers in PCI I/O space.
IO/MEM
IO Space Indicator. This bit is hard-wired to a logic one to indicate PCI I/O space.
RES
Reserved. This bit is hard-wired to zero.
BASE
Base Address. These bits define the I/O space base address of the MPIC control registers. The
MIBAR decoder is disabled when the BASE value is zero.
2.5.2.6 MPIC Memory Base Address Register
Table 2-58 MPIC I/O Base Address Register
Offset
$10
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MIBAR
BASE
RE
S
IO/MEM
Operation R/W R
R R
Reset $0000 $0000
0 1
Table 2-59 MPIC Memory Base Address Register
Offset $14
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MMBAR