Artesyn MVME5100, Programmer'S Reference Manual, Page: 260 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
260
3.3.3.23 SDRAM Enable and Size Register (Blocks E,F,G,H)
Writes to this register must be enveloped by a period of time in which no accesses to SDRAM
occur. The requirements of the envelope are that all SDRAM accesses must have completed
before the write starts and none should begin until after the write is done. A simple way to do
this is to perform at least two read accesses to this or another register before and after the
write.
Additionally, sometime during the envelope, before or after the write, all of the SDRAMs’ open
pages must be closed and the Hawk’s open page tracker reset. The way to do this is to allow
enough time for at least one SDRAM refresh to occur by waiting for the 32-bit Counter (see
section further on) to increment at least 100 times. The wait period needs to happen during
the envelope.
ram e/f/g/h en
ram e/f/g/h en enables accesses to the corresponding block of SDRAM when set, and disables
them when cleared.
ram e/f/g/h siz0-3
Table 3-41 SDRAM Enable and Size Register (Blocks E,F,G,H)
Address $FEF800C0
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
ram e e
n
0 0 0 ram e si
z0
ram e si
z1
ram e si
z2
ram e si
z3
ram f e
n
0 0 0 ram f si
z0
ram f si
z1
ram f si
z2
ram f si
z3
ram g e
n
0 0 0 ram g ram g si
z1
ram g si
z2
ram g si
z3
ram h e
n
0 0 0 ram h si
z0
ram h si
z1
ram h si
z2
ram h si
z3
Operation
R/W R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W
Reset
0 PL X X X 0 P 0 P 0 P 0 P 0 PL X X X 0 P 0 P 0 P 0 P 0 PL X X X 0 P 0 P 0 P 0 P 0 PL X X X 0 P 0 P 0 P 0 P
Note that ram a/b/c/d en are located at $FEF80010 (refer to SDRAM Enable and Size Register
(Blocks A, B, C, D) on page 234 ). They operate the same for blocks A-D as these bits do for
blocks E-H.