Artesyn MVME5100, Programmer'S Reference Manual, Page: 239 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
239
7.8us corresponds to 64ms per 8192 rows and 15.6us corresponds to 64ms per 4096 rows.
por
por is set by the occurrence of power up reset. It is cleared by writing a one to it. Writing a 0 to
it has no effect.
3.3.3.6 ECC Control Register
refdis
When set, refdis causes the refresher and all of its associated counters and state machines to be
cleared and maintained that way until refdis is removed (cleared). If a refresh cycle is in process
when refdis is updated by a write to this register, the update does not take effect until the
refresh cycle has completed. This prevents the generation of illegal cycles to the SDRAM when
refdis is updated.
rwcb
MVME5100 boards are 100 MHz SBCs.
Table 3-19 ECC Control Register
Address $FEF80028
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
0 0 0 0 0 re
fd
is
rwcb de
rc
0 0 0 ap
ie
n
sc
ie
n
dp
ie
n
si
en
mi
en
in
t
0 0 0 0 0 0 0 mbe_m
e
Operation
R R R R R R/W R/W R/W R R R R/W R/W R/W R/W R/W R/C
READ ZERO
R R R R R R R R/W
Reset
X X X X X 0 PL 0 PL 1 PL X X X 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL X X X X X X X 0 PL