Artesyn MVME5100, Programmer'S Reference Manual, Page: 69 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
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For each map, there is an associated set of attributes. These attributes are used to enable read
accesses, enable write accesses, enable write posting, and define the PCI transfer
characteristics.
Each map decoder also includes a programmable 16-bit address offset. The offset is added to
the 16 most significant bits of the PPC address, and the result is used as the PCI address. This
offset allows PCI devices to reside at any PCI address, independent of the PPC address map.
An example of this is shown in the following figure:
Care should be taken to ensure that all programmable decoders decode unique address ranges
since overlapping address ranges will lead to undefined operation.
2.3.2.2 PPC Slave
The PPC slave provides the interface between the PPC bus and the PPC FIFO. The PPC slave is
responsible for tracking and maintaining coherency in the PPC60x processor bus protocol. The
actions taken by the PPC Slave to service a transaction are dependent upon whether the
transaction is posted or compelled. During compelled transactions, such as a read or a non-
posted single beat write, the PPC Slave will hold off asserting AACK_ and TA_ until after the
transaction has completed on the PCI bus. This has the effect of removing all levels of pipelining
Figure 2-3 PPC to PCI Address Translation