Artesyn MVME5100, Programmer'S Reference Manual, Page: 120 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
120
2.4.15.1 External Interrupt Service
The following summarizes how an external interrupt is serviced:

An external interrupt occurs.

The processor state is saved in the machine status save/restore registers. A new value is
loaded into the Machine State Register (MSR). The External Interrupt Enable bit in the new
MSR (MSRee) is set to zero. Control is transferred to the O/S external interrupt handler.

The external interrupt handler calculates the address of the Interrupt Acknowledge
register for this processor (MPIC Base A 0x200A0) + (processor ID shifted left 12
bits).

The external interrupt handler issues an Interrupt Acknowledge request to read the
interrupt vector from the Hawk’s MPIC. If the interrupt vector indicates the interrupt
source is the 8259, the interrupt handler issues a second Interrupt Acknowledge request
to read the interrupt vector from the 8259. The Hawk’s MPIC does not interact with the
vector fetch from the 8259.

The interrupt handler saves the processor state and other interruptspecific information in
system memory and re-enables for external interrupts (the MSRee bit is set to 1). MPIC
blocks interrupts from sources with equal or lower priority until an End-of-Interrupt is
received for that interrupt source. Interrupts from higher priority interrupt sources
continue to be enabled. If the interrupt source is the 8259, the interrupt handler issues an
EOI request to the MPIC. This resets the In-Service bit for the 8259 within the MPIC and
allows it to recognize higher priority interrupt requests, if any, from the 8259. If none of
the nested interrupt modes of the 8259 are enabled, the interrupt handler issues an EOI
request to the 8259.
– The device driver interrupt service routine associated with this interrupt vector is
invoked.
– If the interrupt source was not the 8259, the interrupt handler issues an EOI request for
this interrupt vector to the MPIC. If the interrupt source was the 8259 and any of the
nested interrupt modes of the 8259 are enabled, the interrupt handler issues an EOI
request to the 8259.
Normally, interrupts from ISA devices are connected to the 8259 interrupt controller. ISA
devices typically rely on the 8259 Interrupt Acknowledge to flush buffers between the ISA
device and system memory. If interrupts from ISA devices are directly connected to the MPIC
(bypassing the 8259), the device driver interrupt service routine must read status from the ISA
device to ensure buffers between the device and system memory are flushed.