Artesyn MVME5100, Programmer'S Reference Manual, Page: 264 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
264
Together tras0,1 determine the minimum number of clock cycles that the SMC assumes the
SDRAM requires to satisfy its tRAS parameter. These bits are encoded as follows:
swr_dpl
swr_dpl causes the SMC to always wait until four clocks after the write command portion of a
single write before allowing a precharge to occur. This function may not be required. If such is
the case, swr_dpl can be cleared by software.
tdp
tdp determines the minimum number of clock cycles that the SMC assumes the SDRAM
requires to satisfy its Tdp parameter. When tdp is 0, the minimum time provided for Tdp is 1
clock. When tdp is 1, the minimum is 2 clocks.
trp
trp determines the minimum number of clock cycles that the SMC assumes the SDRAM
requires to satisfy its Trp parameter. When trp is 0, the minimum time provided for Trp is 2
clocks. When trp is 1, the minimum is 3 clocks.
trcd
trcd determines the minimum number of clock cycles that the SMC assumes the SDRAM
requires to satisfy its Trcd parameter. When trcd is 0, the minimum time provided for Trcd is 2
clocks. When trcd is 1, the minimum is 3 clocks.
Table 3-45 tras Encoding
tras0,1 Minimum Clocks for tras
%00 4
%01 5
%10 6
%11 7