Artesyn MVME5100, Programmer'S Reference Manual, Page: 209 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
209
information related to the memory subsystem even when the power is removed from the
system. Each slave device connected to the I
2
C bus is software addressable by a unique
address. The number of interfaces connected to the I
2
C bus is solely dependent on the bus
capacitance limit of 400pF.
For I
2
C bus programming, the ASIC is the only master on the bus and the serial EEPROM devices
are all slaves. The I
2
C bus supports 7-bit addressing mode and transmits data one byte at a time
in a serial fashion with the most significant bit (MSB) being sent out first. Five registers are
required to perform the I
2
C bus data transfer operations. These are the I
2
C Clock Prescaler
Register, I
2
C Control Register, I
2
C Status Register, I
2
C Transmitter Data Register, and I
2
C
Receiver Data Register.
The I
2
C SDA is an open-drain bi-directional line on which data can be transferred at a rate up to
100 Kbits/s in the standard mode, or up to 400 kbits/s in the fast mode. The I
2
C serial clock
(SCL) is programmable via I2_PRESCALE_VAL bits in the I
2
C Clock Prescaler Register. The I
2
C
clock frequency is determined by the following formula:
I
2
C CLOCK = SYSTEM CLOCK / (I2_PRESC1) / 2
The I
2
C bus has the ability to perform byte write, page write, current address read, random
read, and sequential read operations.
The section discusses the following topics:

I2C Byte Write on page 209

I2C Random Read on page 213

I2C Current Address Read on page 216

I2C Page Write on page 219

I2C Sequential Read on page 222
3.2.6.1 I
2
C Byte Write
The I
2
C Status Register contains the i2_cmplt bit which is used to indicate if the I
2
C master
controller is ready to perform an operation. Therefore, the first step in the programming
sequence should be to test the i2_cmplt bit for the operation-complete status. The next step
is to initiate a start sequence by first setting the i2 start and i2 enbl bits in the I
2
C Control
Register and then writing the device address (bits 7-1) and write bit (bit 0=0) to the I
2
C
Transmitter Data Register. The i2_cmplt bit will be automatically clear with the write cycle to
the I
2
C Transmitter Data Register. The I
2
C Status Register must now be polled to test the