Artesyn MVME5100, Programmer'S Reference Manual, Page: 235 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
235
These control bits define the size of their corresponding block of SDRAM. Table 3-10 shows the
block configuration assumed by the SMC for each value of ram siz0-ram siz3. Note that ram
e/f/g/h size0-3 are located at $FEF800C0. They operate identically for blocks E-H as these bits
do for blocks A-D.
Table 3-15 Block_A/B/C/D/E/F/G/H Configurations
ram a-h siz0-3
Component
Configuration
Number of
SDRAM
Components
In the Block
Block SIZE
SDRAM
Technology
%0000 - - 0MBytes -
%0001 4Mx16 5 32MBytes 64Mbit
%0010 8Mx8 9 64MBytes 64Mbit
%0011 8Mx16 5 64MBytes 128Mbit
%0100 16Mx4 18 128MBytes 64Mbit
%0101 16Mx8 9 128MBytes 128Mbit
%0110 16Mx16 5 128MBytes 256Mbit
%0111 32Mx4 18 256MBytes 128Mbit
%1000 32Mx8 9 256MBytes 256Mbit
%1001 64Mx4 18 512MBytes 256Mbit
%1010
-
%1111 Reserved - - -
All SDRAM components should be organized with 4 internal banks.
When DIMMs are used, the Component Configuration refers to the configuration of the
devices used on the DIMMs.
It is important that all of the ram a/b/c/d/e/f/g/h siz0-3 bits be set to accurately match the
actual size of their corresponding blocks. This includes clearing them to binary 00000 if their
corresponding blocks are not present. Failure to do so will cause problems with addressing
and with scrub logging.