Artesyn MVME5100, Programmer'S Reference Manual, Page: 122 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B )
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2.4.16.2 Dynamically Changing I/O Interrupt Configuration
The interrupt controller provides a mechanism for safely changing the vector, priority, or
destination of I/O interrupt sources. This is provided to support systems which allow dynamic
configuration of I/O devices. In order to change the vector, priority, or destination of an active
interrupt source, the following sequence should be performed:

Mask the source using the MASK bit in the vector/priority register.

Wait for the activity bit (ACT) for that source to be cleared.

Make the desired changes.

Unmask the source.
This sequence ensures that the vector, priority, destination, and mask information remain valid
until all processing of pending interrupts is complete.
2.4.16.3 EOI Register
Each processor has a private EOI register which is used to signal the end of processing for a
particular interrupt event. If multiple nested interrupts are in service, the EOI command
terminates the interrupt service of the highest priority source. Once an interrupt is
acknowledged, only sources of higher priority will be allowed to interrupt the processor until
the EOI command is received. This register should always be written with a value of zero which
is the nonspecific EOI command.
2.4.16.4 Interrupt Acknowledge Register
Upon receipt of an interrupt signal, the processor may read this register to retrieve the vector
of the interrupt source which caused the interrupt.
2.4.16.5 8259 Mode
The 8259 mode bits control the use of an external 8259 pair for PC-AT compatibility. Following
reset, this mode is set for pass through which essentially disables the advanced controller and
passes an 8259 input on external interrupt source 0 directly through to processor zero. During
interrupt controller initialization, this channel should be programmed for mixed mode in order
to take advantage of the interrupt delivery modes.