Artesyn MVME5100, Programmer'S Reference Manual, Page: 253 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
253
rom_b_spd0,1
rom_b_spd0,1 determine the access timing used for ROM/Flash Block B. Refer to the table
above.
Writes that change these bits must be enveloped by a period of time in which no accesses to
ROM/Flash, Bank B, occur. A simple way to provide the envelope is to perform at least two
accesses to this or another of the SMC’s registers before and after the write.
3.3.3.14 Data Parity Error Log Register
dpelog
dpelog is set when a parity error occurs on the PPC60x data bus during a PPC60x data cycle
whose parity the SMC is qualified to check. It is cleared by writing a one to it or by power-up
reset.
dpe_tt0-4
dpe_tt is the value that was on the TT0-TT4 signals when the dpelog bit was set.
DPE_DP
%11 3 Clock Periods (30ns @100 MHz, 45ns @ 66.67 MHz
Table 3-31 ROM Speed Bit Encoding (continued)
rom_a/b_spd0,1 Approximate ROM Block A/B Device Access Time
Table 3-32 Data Parity Error Log Register
Address
$FEF80068
Bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Name
dpe
log
0 0 dpe_tt0 dpe_tt1 dpe_tt2 dpe_tt3 dpe_tt4
DPE_DP
0 0 0 0 0 0 dpe_ck
all
dpe_me
GWDP
Operation
R/C R R R R R R R
READ ONLY
R R R R R R R/W R/W
READ/WRITE
Reset
0 P
X 0 P 0 P 0 P 0 P 0 P
0 P
X X X X X X 0 PL 0 PL
0 PL