Artesyn MVME5100, Programmer'S Reference Manual, Page: 159 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
159
The MPIC Memory Base Address Register (MMBAR) controls the mapping of the MPIC control
registers in PCI memory space.
IO/MEM
IO Space Indicator. This bit is hard-wired to a logic zero to indicate PCI memory space.
MTYPx
Memory Type. These bits are hard-wired to zero to indicate that the MPIC registers can be
located anywhere in the 32-bit address space.
PRE
Prefetch. This bit is hard-wired to zero to indicate that the MPIC registers are not prefetchable.
BASE
Base Address. These bits define the memory space base address of the MPIC control registers.
The MBASE decoder is disabled when the BASE value is zero.
BASE
PRE MT
YP1
MT
YP0
IO/MEM
Operation R/W R
R R R R
Reset $0000 $0000
0 0 0 0
Table 2-59 MPIC Memory Base Address Register (continued)
Offset $14
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0