Artesyn MVME5100, Programmer'S Reference Manual, Page: 83 / 318

Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
83
Addressing
The PCI Slave will accept any combination of byte enables during read or write cycles. During
write cycles, a discontinuity (i.e., a ‘hole’) in the byte enables forces the PCI Slave to issue a
disconnect. During all read cycles, the PCI Slave returns an entire word of data regardless of the
byte enables. During I/O read cycles, the PCI Slave performs integrity checking of the byte
enables against the address being presented and assert SERR* in the event there is an error.
The PCI Slave only honors the Linear Incrementing addressing mode. The PCI Slave performs a
disconnect with data if any other mode of addressing is attempted.
Device Selection
The PCI slave will always respond valid decoded cycles as a medium responder.
Target Initiated Termination
Reserved No
Reserved No
Memory Read Yes
Memory Write Yes
Reserved No
Reserved No
Configuration Read Yes
Configuration Write Yes
Memory Read Multiple Yes
Dual Address Cycle No
Memory Read Line Yes
Memory Write and
Invalidate Yes
Table 2-8 PCI Slave Response Command Types (continued)
Command Type Slave Response?