Artesyn MVME5100, Programmer'S Reference Manual, Page: 219 / 318

System Memory Controller (SMC)
MVME5100 Single Board Computer Programmer’s Reference (6806800H17B)
219
3.2.6.4 I
2
C Page Write
The I
2
C page write is initiated the same as the I
2
C byte write, but instead of sending a stop
sequence after the first data word, the I
2
C master controller will transmit more data words
before a stop sequence is generated. The first step in the programming sequence should be to
test the i2_cmplt bit for the operation-complete status. The next step is to initiate a start
sequence by first setting the i2_start and i2_enbl bits in the I
2
C Control Register and then
writing the device address (bits 7-1) and write bit (bit 0=0) to the I
2
C Transmitter Data Register.
The i2_cmplt bit will be automatically clear with the write cycle to the I
2
C Transmitter Data
Register. The I
2
C Status Register must now be polled to test the i2_cmplt and i2_ackin bits. The
i2_cmplt bit becomes set when the device address and write bit have been transmitted, and
the i2_ackin bit provides status as to whether or not a slave device acknowledged the device
address. With the successful transmission of the device address, the initial word address will be
loaded into the I
2
C Transmitter Data Register to be transmitted to the slave device. Again,
i2_cmplt and i2_ackin bits must be tested for proper response. After the initial word address is
successfully transmitted, the first data word loaded into the I
2
C Transmitter Data Register will
be transferred to the initial address location of the slave device. After i2_cmplt and i2_ackin
bits have been tested for proper response, the next data word loaded into the I
2
C Transmitter
Data Register will be transferred to the next address location of the slave device, and so on,
until the block transfer is complete. A stop sequence then must be transmitted to the slave
device by first setting the i2_stop and i2_enbl bits in the I
2
C Control Register and then writing
a dummy data (data=don’t care) to the I
2
C Transmitter Data Register. The I
2
C Status Register